LTC1871-7 [Linear Systems]
PolyPhase Synchronous Boost Controller; 多相同步升压控制器
| 型号： | LTC1871-7 |
| 厂家： | 
Linear Systems |
| 描述： | PolyPhase Synchronous Boost Controller |
| 文件： | 总36页 (文件大小：358K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3787
PolyPhase Synchronous
Boost Controller
FEATURES
DESCRIPTION
The LTC®3787 is a high performance PolyPhase® single
outputsynchronousboostconvertercontrollerthatdrives
two N-channel power MOSFET stages out-of-phase.
Multiphase operation reduces input and output capacitor
requirements and allows the use of smaller inductors than
the single-phase equivalent. Synchronous rectification in-
creasesefficiency,reducespowerlossesandeasesthermal
requirements, enabling high power boost applications.
n
2-Phase Operation Reduces Required Input and
Output Capacitance and Power Supply Induced Noise
n
Synchronous Operation for Highest Efficiency and
Reduced Heat Dissipation
n
Wide V Range: 4.5V to 38V (40V Abs Max) and
IN
Operates Down to 2.5V After Start-Up
Output Voltage Up to 60V
n
n
n
n
n
n
n
n
n
n
n
±±1 ±.200V Reference Voltage
R
or Inductor DCR Current Sensing
SENSE
A 4.5V to 38V input supply range encompasses a wide
range of system architectures and battery chemistries.
When biased from the output of the boost converter or
another auxiliary supply, the LTC3787 can operate from
an input supply as low as 2.5V after start-up. The operat-
ing frequency can be set for a 50kHz to 900kHz range or
synchronized to an external clock using the internal PLL.
PolyPhase operation allows the LTC3787 to be configured
for 2-, 3-, 4-, 6- and 12-phase operation.
±001 Duty Cycle Capability for Synchronous MOSFET
Low Quiescent Current: 135μA
Phase-Lockable Frequency (75kHz to 850kHz)
Programmable Fixed Frequency (50kHz to 900kHz)
Power Good Output Voltage Monitor
Low Shutdown Current, I < 8ꢀA
Q
Internal LDO Powers Gate Drive from VBIAS or EXTV
CC
Thermally Enhanced Low Profile 28-Pin 4mm × 5mm
QFN Package and Narrow SSOP Package
The SS pin ramps the output voltage during start-up. The
PLLIN/MODE pin selects Burst Mode® operation, pulse-
skipping mode or forced continuous mode at light loads.
APPLICATIONS
n
Industrial
L, LT, LTC, LTM, Linear Technology, the Linear logo, Burst Mode, OPTI-LOOP and PolyPhase
n
are registered trademarks and No R
and ThinSOT are trademarks of Linear Technology
Automotive
SENSE
Corporation. All other trademarks are the property of their respective owners. Protected by
U. S. Patents, including 5408150, 5481178, 5705919, 5929620, 6144194, 6177787, 6580258.
n
Medical
Military
n
TYPICAL APPLICATION
Efficiency and Power Loss
vs Output Current
±2V to 24V/±0A 2-Phase Synchronous Boost Converter
V
4.5V TO 24V START-UP VOLTAGE
IN
OPERATES THROUGH TRANSIENTS DOWN TO 2.5V
V
IN
100
90
10000
1000
100
10
80
4.7ꢀF
TG2
4.7ꢀF
47ꢀF
4mΩ
4mΩ
70
TG1 VBIAS INTV
BOOST1
CC
60
50
3.3ꢀH
3.3ꢀH
BOOST2
SW2
0.1ꢀF
0.1ꢀF
V
OUT
24V AT 10A
40
30
20
10
0
SW1
LTC3787
BG1
SENSE1
SENSE1
VFB
FREQ
PLLIN/MODE
ITH SS SGND
BG2
+
V
V
= 12V
IN
OUT
1
–
+
= 24V
232k
SENSE2
Burst Mode OPERATION
FIGURE 10 CIRCUIT
–
SENSE2
0.1
PGND
0.00001 0.0001 0.001 0.01
0.1
1
10
OUTPUT CURRENT (A)
3787 TA01b
15nF
8.66k
220ꢀF
12.1k
BURST EFFICIENCY
BURST LOSS
100pF
0.1ꢀF
3787 TA01a
3787fc
1
LTC3787
(Notes ±, 3)
ABSOLUTE MAXIMUM RATINGS
EXTV ........................................................ –0.3V to 6V
VBIAS ........................................................ –0.3V to 40V
BOOST1 and BOOST2................................ –0.3V to 76V
SW1 and SW2............................................ –0.3V to 70V
RUN ............................................................. –0.3V to 8V
Maximum Current Sourced into Pin
CC
+
–
+
–
SENSE1 , SENSE1 , SENSE2 , SENSE2 ... –0.3V to 40V
+
–
+
–
(SENSE1 -SENSE1 ), (SENSE2 - SENSE2 )...–0.3Vto 0.3V
ILIM, SS, ITH, FREQ, PHASMD, VFB.....–0.3V to INTV
CC
Operating Junction Temperature
Range (Note 2)........................................–55°C to 150°C
Storage Temperature Range .................. –65°C to 150°C
From Source >8V..............................................100ꢀA
PGOOD, PLLIN/MODE ................................. –0.3V to 6V
INTV , (BOOST1 - SW1), (BOOST2 - SW2)...–0.3V to 6V
CC
PIN CONFIGURATION
TOP VIEW
TOP VIEW
1
2
PGOOD
SW1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
ILIM
+
SENSE1
–
28 27 26 25 24 23
3
TG1
SENSE1
FREQ
PHASMD
CLKOUT
PLLIN/MODE
SGND
1
2
3
4
5
6
7
8
22
BOOST1
4
BOOST1
BG1
FREQ
PHASMD
CLKOUT
PLLIN/MODE
SGND
21 BG1
5
20 VBIAS
19 PGND
6
VBIAS
PGND
29
GND
7
18 EXTV
CC
CC
8
EXTV
CC
17 INTV
16 BG2
RUN
9
INTV
CC
RUN
SS
10
11
12
13
14
BG2
SS
–
BOOST2
15
SENSE2
–
BOOST2
TG2
SENSE2
9
10 11 12 13 14
UFD PACKAGE
+
SENSE2
SW2
NC
VFB
ITH
28-LEAD (4mm s 5mm) PLASTIC QFN
GN PACKAGE
28-LEAD PLASTIC SSOP
T
= 125°C, θ = 43°C/W
JMAX
JA
EXPOSED PAD (PIN 29) IS GND, MUST BE CONNECTED TO GND
T
= 125°C, θ = 90°C/W
JA
JMAX
ORDER INFORMATION
LEAD FREE FINISH
LTC3787EUFD#PBF
LTC3787IUFD#PBF
LTC3787HUFD#PBF
LTC3787MPUFD#PBF
LTC3787EGN#PBF
LTC3787IGN#PBF
LTC3787HGN#PBF
LTC3787MPGN#PBF
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC3787EUFD#TRPBF
LTC3787IUFD#TRPBF
LTC3787HUFD#TRPBF
3787
3787
3787
–40°C to 125°C
–40°C to 125°C
–40°C to 150°C
–55°C to 150°C
–40°C to 125°C
–40°C to 125°C
–40°C to 150°C
–55°C to 150°C
28-Lead (4mm × 5mm) Plastic QFN
28-Lead (4mm × 5mm) Plastic QFN
28-Lead (4mm × 5mm) Plastic QFN
28-Lead (4mm × 5mm) Plastic QFN
28-Lead Plastic SSOP
LTC3787MPUFD#TRPBF 3787
LTC3787EGN#TRPBF
LTC3787IGN#TRPBF
LTC3787HGN#TRPBF
LTC3787MPGN#TRPBF
LTC3787GN
LTC3787GN
LTC3787GN
LTC3787GN
28-Lead Plastic SSOP
28-Lead Plastic SSOP
28-Lead Plastic SSOP
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
3787fc
2
LTC3787
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C, VBIAS = ±2V, unless otherwise noted (Note 2).
SYMBOL
Main Control Loop
VBIAS Chip Bias Voltage Operating Range
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
4.5
38
1.212
50
V
V
l
V
Regulated Feedback Voltage
Feedback Current
I
TH
= 1.2V (Note 4)
1.188
1.200
5
FB
I
FB
(Note 4)
nA
%/V
%
V
V
Reference Line Voltage Regulation
VBIAS = 6V to 38V
Measured in Servo Loop;
0.002
0.01
0.02
0.1
REFLNREG
LOADREG
l
l
Output Voltage Load Regulation
(Note 4)
ΔI Voltage = 1.2V to 0.7V
TH
Measured in Servo Loop;
–0.01
2
–0.1
%
ΔI Voltage = 1.2V to 2V
TH
g
Error Amplifier Transconductance
I
TH
= 1.2V
mmho
m
I
Q
Input DC Supply Current
Pulse-Skipping or Forced Continuous Mode
Sleep Mode
(Note 5)
RUN = 5V; V = 1.25V (No Load)
1.2
135
8
mA
ꢀA
ꢀA
FB
RUN = 5V; V = 1.25V (No Load)
300
20
FB
Shutdown
RUN = 0V
l
l
UVLO
INTV Undervoltage Lockout Thresholds
V
V
Ramping Up
Ramping Down
4.1
3.8
4.3
V
V
CC
INTVCC
INTVCC
3.6
l
V
V
RUN Pin ON Threshold
RUN Pin Hysteresis
V
Rising
1.18
1.28
100
4.5
0.5
10
1.38
V
mV
ꢀA
RUN
RUN
RUNHYS
RUNHYS
RUN
I
I
I
RUN Pin Hysteresis Current
RUN Pin Current
V
V
V
> 1.28V
RUN
< 1.28V
ꢀA
RUN
Soft-Start Charge Current
Maximum Current Sense Threshold
= GND
7
13
ꢀA
SS
SS
l
l
l
V
V
FB
V
FB
V
FB
= 1.1V, I = INTV
90
68
42
100
75
50
110
82
56
mV
mV
mV
SENSE1,2(MAX)
SENSE(MATCH)
SENSE(CM)
LIM
LIM
LIM
CC
= 1.1V, I = Float
= 1.1V, I = GND
l
l
l
V
Matching Between V
SENSE2(MAX)
and
V
V
V
= 1.1V, I = INTV
–12
–10
–9
0
0
0
12
10
9
mV
mV
mV
SENSE1(MAX)
FB
FB
FB
LIM
LIM
LIM
CC
V
= 1.1V, I = Float
= 1.1V, I = GND
V
I
SENSE Pins Common Mode Range (BOOST
2.5
38
V
Converter Input Supply Voltage V )
IN
+
SENSE Pin Current
V
V
C
C
C
C
= 1.1V, I = Float
200
300
1
ꢀA
ꢀA
ns
ns
ns
ns
Ω
+
–
SENSE1,2
FB
LIM
–
I
t
t
t
t
SENSE Pin Current
= 1.1V, I = Float
LIM
SENSE1,2
r(TG1,2)
f(TG1,2)
r(BG1,2)
r(BG1,2)
FB
Top Gate Rise Time
= 3300pF (Note 6)
= 3300pF (Note 6)
= 3300pF (Note 6)
= 3300pF (Note 6)
20
20
LOAD
LOAD
LOAD
LOAD
Top Gate Fall Time
Bottom Gate Rise Time
20
Bottom Gate Fall Time
20
R
R
R
R
Top Gate Pull-Up Resistance
Top Gate Pull-Down Resistance
Bottom Gate Pull-Up Resistance
Bottom Gate Pull-Down Resistance
1.2
1.2
1.2
1.2
70
UP(TG1,2)
DN(TG1,2)
UP(TG1,2)
DN(TG1,2)
D(TG/BG)
Ω
Ω
Ω
t
t
Top Gate Off to Bottom Gate On Switch-On
Delay Time
C
C
= 3300pF (Each Driver)
= 3300pF (Each Driver)
ns
LOAD
LOAD
Bottom Gate Off to Top Gate On Switch-On
Delay Time
70
ns
D(BG/TG)
DF
Maximum BG Duty Factor
Minimum BG On-Time
96
%
BG1,2(MAX)
t
(Note 7)
110
ns
ON(MIN)
3787fc
3
LTC3787
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C, VBIAS = ±2V, unless otherwise noted (Note 2).
SYMBOL
PARAMETER
CONDITIONS
MIN
5.2
5.2
4.5
TYP
MAX
UNITS
INTV Linear Regulator
CC
INTVCC(VIN)
V
Internal V Voltage
6V < V
< 38V, V = 0
EXTVCC
5.4
0.5
5.4
0.5
4.8
250
5.6
2
V
%
V
CC
BIAS
VLDO INT
INTV Load Regulation
I
CC
= 0mA to 50mA
CC
V
Internal V Voltage
V = 6V
EXTVCC
5.6
2
INTVCC(EXT)
CC
VLDO EXT
INTV Load Regulation
I
CC
= 0mA to 40mA, V = 6V
EXTVCC
%
V
CC
l
V
V
EXTV Switchover Voltage
EXTV Ramping Positive
5
EXTVCC
LDOHYS
CC
CC
EXTV Hysteresis
mV
CC
Oscillator and Phase-Locked Loop
f
Programmable Frequency
R
FREQ
R
FREQ
R
FREQ
= 25k
= 60k
= 100k
105
400
760
kHz
kHz
kHz
PROG
335
465
f
f
f
Lowest Fixed Frequency
Highest Fixed Frequency
Synchronizable Frequency
V
V
= 0V
320
488
75
350
535
380
585
850
kHz
kHz
kHz
LOW
HIGH
SYNC
FREQ
FREQ
= INTV
CC
l
PLLIN/MODE = External Clock
PGOOD Output
V
PGOOD Voltage Low
PGOOD Leakage Current
PGOOD Trip Level
I
= 2mA
= 5V
0.2
0.4
1
V
PGL
PGOOD
I
V
ꢀA
PGOOD
PGOOD
V
V
with Respect to Set Regulated Voltage
FB
PGOOD
V
Ramping Negative
–12
8
–10
2.5
–8
12
%
%
FB
Hysteresis
V
Ramping Positive
10
2.5
%
%
FB
Hysteresis
t
PGOOD Delay
PGOOD Going High to Low
25
ꢀs
PGOOD(DELAY)
BOOST± and BOOST2 Charge Pump
I
BOOST Charge Pump Available Output
Current
V
= 12V; V
– V = 4.5V;
SW1,2
55
ꢀA
BOOST1,2
SW1,2
BOOST1,2
FREQ = 0V, Forced Continuous or
Pulse-Skipping Mode
Note ±: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
temperature (T , in °C) and power dissipation (P , in Watts) according to
A D
the formula: T = T + (P • θ ), where θ = 43°C/W for the QFN package
J
A
D
JA
JA
and θ = 90°C/W for the SSOP package.
JA
Note 3: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. The maximum
rated junction temperature will be exceeded when this protection is active.
Continuous operation above the specified absolute maximum operating
junction temperature may impair device reliability or permanently damage
the device.
Note 2: The LTC3787 is tested under pulsed load conditions such that
T ≈ T . The LTC3787E is guaranteed to meet specifications from
J
A
0°C to 85°C junction temperature. Specifications over the –40°C to
125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LTC3787I is guaranteed over the –40°C to 125°C operating junction
temperature range, the LTC3787H is guaranteed over the –40°C to 150°C
operating temperature range and the LTC3787MP is tested and guaranteed
over the full –55°C to 150°C operating junction temperature range. High
junction temperatures degrade operating lifetimes; operating lifetime
is derated for junction temperatures greater than 125°C. Note that the
maximum ambient temperature consistent with these specifications is
determined by specific operating conditions in conjunction with board
layout, the rated package thermal impedance and other environmental
Note 4: The LTC3787 is tested in a feedback loop that servos V to the
FB
output of the error amplifier while maintaining I at the midpoint of the
TH
current limit range.
Note 5: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency.
Note 6: Rise and fall times are measured using 10% and 90% levels. Delay
times are measured using 50% levels.
Note 7: see Minimum On-Time Considerations in the Applications
Information section.
factors. The junction temperature (T , in °C) is calculated from the ambient
J
3787fc
4
LTC3787
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency and Power Loss
vs Output Current
Efficiency and Power Loss
vs Output Current
100
90
10000
1000
100
10
100
90
10000
1000
100
10
80
80
70
70
60
50
60
50
40
30
20
10
0
40
30
20
10
0
V
V
= 12V
OUT
1
IN
1
V
V
= 12V
IN
OUT
= 24V
= 24V
Burst Mode OPERATION
FIGURE 10 CIRCUIT
FIGURE 10 CIRCUIT
0.1
0.1
0.01
0.1
1
10
0.00001 0.0001 0.001 0.01
0.1
1
10
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
3787 G01
3787 G02
BURST EFFICIENCY BURST LOSS
BURST EFFICIENCY
BURST LOSS
PULSE-SKIPPING
EFFICIENCY
PULSE-SKIPPING
LOSS
FORCED CONTINUOUS
MODE EFFICIENCY
FORCED CONTINUOUS
MODE LOSS
Load Step
Forced Continuous Mode
Efficiency vs Load Current
100
99
98
97
96
95
94
93
92
91
90
V
I
= 12V
= 2A
IN
LOAD
LOAD STEP
5A/DIV
FIGURE 10 CIRCUIT
V
= 24V
OUT
V
= 12V
OUT
INDUCTOR
CURRENT
5A/DIV
V
OUT
500mV/DIV
3787 G04
V
V
= 12V
200ꢀs/DIV
0
5
15
INPUT VOLTAGE (V)
20
25
10
IN
OUT
= 24V
3787 G03
LOAD STEP FROM 100mA TO 5A
FIGURE 10 CIRCUIT
Load Step
Pulse-Skipping Mode
Load Step
Burst Mode Operation
LOAD STEP
5A/DIV
LOAD STEP
5A/DIV
INDUCTOR
CURRENT
5A/DIV
INDUCTOR
CURRENT
5A/DIV
V
OUT
V
OUT
500mV/DIV
500mV/DIV
3787 G05
3787 G06
V
V
= 12V
200ꢀs/DIV
V
V
= 12V
200ꢀs/DIV
IN
OUT
IN
OUT
= 24V
= 24V
LOAD STEP FROM 100mA TO 5A
FIGURE 10 CIRCUIT
LOAD STEP FROM 100mA TO 5A
FIGURE 10 CIRCUIT
3787fc
5
LTC3787
TYPICAL PERFORMANCE CHARACTERISTICS
Inductor Current at Light Load
Soft Start-Up
FORCED
CONTINUOUS MODE
V
OUT
Burst Mode
OPERATION
5A/DIV
5V/DIV
PULSE-SKIPPING
MODE
0V
3787 G07
3787 G08
V
V
LOAD
= 12V
5ꢀs/DIV
V
V
= 12V
20ms/DIV
IN
IN
OUT
= 24V
= 24V
OUT
I
= 200ꢀA
FIGURE 10 CIRCUIT
FIGURE 10 CIRCUIT
Regulated Feedback Voltage
vs Temperature
Soft-Start Pull-Up Current
vs Temperature
11.0
10.5
10.0
9.5
1.212
1.209
1.206
1.203
1.200
1.197
1.194
1.191
1.188
9.0
–60
–35 –10
40 65 90 115 140
TEMPERATURE (°C)
–60
15
–35 –10
40 65 90 115 140
TEMPERATURE (°C)
15
3787 G09
3787 G10
Shutdown Current vs Temperature
Shutdown Current vs Input Voltage
11.0
10.5
10.0
9.5
9.0
8.5
8.0
7.5
7.0
6.5
6.0
5.5
5.0
20
15
10
5
V
= 12V
IN
0
–35 –10
40 65 90 115 140
TEMPERATURE (°C)
–60
15
5
10
20 25 30 35 40
15
INPUT VOLTAGE (V)
0
3787 G11
3787 G12
3787fc
6
LTC3787
TYPICAL PERFORMANCE CHARACTERISTICS
Shutdown (RUN) Threshold
vs Temperature
Quiescent Current vs Temperature
180
170
160
150
140
130
120
110
1.40
1.35
1.30
1.25
1.20
1.15
1.10
V
V
= 12V
IN
FB
= 1.25V
RUN = GND
RUN RISING
RUN FALLING
–35 –10
40 65 90 115 140
TEMPERATURE (°C)
–35 –10
40 65 90 115 140
15
TEMPERATURE (°C)
–60
15
–60
3787 G13
3787 G14
Undervoltage Lockout Threshold
vs Temperature
INTVCC Line Regulation
4.4
4.3
4.2
4.1
4.0
3.9
3.8
3.7
3.6
3.5
3.4
5.5
5.4
5.3
5.2
5.1
5.0
4.9
4.8
4.7
4.6
4.5
INTV RISING
CC
INTV FALLING
CC
–35 –10
40 65 90 115 140
–60
15
5
10
20 25 30 35 40
15
INPUT VOLTAGE (V)
0
TEMPERATURE (°C)
3787 G15
3787 G16
EXTVCC Switchover and INTVCC
Voltages vs Temperature
INTVCC vs INTVCC Load Current
6.0
5.8
5.6
5.4
5.2
5.0
4.8
4.6
4.4
4.2
4.0
5.50
5.45
5.40
5.35
5.30
5.25
5.20
5.15
5.10
5.05
5.00
V
= 12V
IN
INTV
CC
EXTV = 0V
CC
EXTV RISING
CC
EXTV = 6V
CC
EXTV FALLING
CC
–35 –10
40 65 90 115 140
15
TEMPERATURE (°C)
–60
40 60 80 100 120
200
0
20
140 160 180
INTV LOAD CURRENT (mA)
CC
3787 G18
3787 G17
3787fc
7
LTC3787
TYPICAL PERFORMANCE CHARACTERISTICS
Oscillator Frequency
vs Temperature
Oscillator Frequency
vs Input Voltage
360
358
356
354
352
350
348
346
344
342
340
600
550
500
450
400
350
300
FREQ = GND
FREQ = INTV
CC
FREQ = GND
5
10
20
25
30
35
40
15
–35 –10
40 65 90 115 140
–60
15
INPUT VOLTAGE (V)
TEMPERATURE (°C)
3787 G20
3787 G19
SENSE Pin Input Current
vs Temperature
Maximum Current Sense
Threshold vs ITH Voltage
120
100
80
260
240
220
200
180
160
140
120
100
80
V
I
= 12V
SENSE
LIM
= FLOAT
+
SENSE PIN
PULSE-SKIPPING MODE
Burst Mode
OPERATION
60
40
20
I
= GND
LIM
0
I
= FLOAT
LIM
LIM
I
= INTV
CC
60
40
20
0
–20
–40
–60
FORCED CONTINUOUS MODE
–
SENSE PIN
0.8
VOLTAGE (V)
1.2 1.4
0
0.2 0.4 0.6
1.0
–35 –10
40 65 90 115 140
15
TEMPERATURE (°C)
–60
I
TH
3787 G22
3787 G21
SENSE Pin Input Current
vs VSENSE Voltage
SENSE Pin Input Current
vs ITH Voltage
260
240
220
200
180
160
140
120
100
80
260
240
220
200
180
160
140
120
100
80
V
= 12V
+
SENSE
I
= INTV
CC
I
= INTV
CC
SENSE PIN
LIM
LIM
I
= FLOAT
I
= FLOAT
= GND
LIM
LIM
I
+
SENSE PIN
LIM
I
= GND
LIM
60
40
20
0
60
40
20
0
I
I
I
= INTV
CC
= FLOAT
= GND
I
I
I
= INTV
CC
= FLOAT
= GND
LIM
LIM
LIM
LIM
LIM
LIM
–
–
SENSE PIN
SENSE PIN
2.5
17.5 22.5 27.5 32.5 37.5
COMMON MODE VOLTAGE (V)
7.5 12.5
0
1
I
1.5
2
2.5
3
0.5
V
VOLTAGE (V)
SENSE
TH
3787 G24
3787 G23
3787fc
8
LTC3787
TYPICAL PERFORMANCE CHARACTERISTICS
Maximum Current Sense
Threshold vs Duty Cycle
Charge Pump Charging Current
vs Operating Frequency
Charge Pump Charging Current
vs Switch Voltage
120
100
80
60
40
20
0
80
70
60
50
40
30
20
10
0
80
70
60
50
40
30
20
10
0
T = –60°C
FREQ = GND
I
= INTV
CC
LIM
FREQ = INTV
CC
T = –45°C
T = 25°C
I
= FLOAT
= GND
LIM
I
LIM
T = 130°C
T = 155°C
20 30 40 50 60
100
70 80 90
0
10
50 150 250 350 450 550 650 750
OPERATING FREQUENCY (kHz)
5
10
15
20
25
30
35
40
DUTY CYCLE (%)
SWITCH VOLTAGE (V)
3787 G26
3787 G27
3787 G25
PIN FUNCTIONS (QFN/SSOP)
FREQ (Pin ±/Pin 4): Frequency Control Pin for the Internal
to be synchronized with the rising edge of the external
clock. When not synchronizing to an external clock, this
input determines how the LTC3787 operates at light loads.
Pulling this pin to ground selects Burst Mode operation.
An internal 100k resistor to ground also invokes Burst
Mode operation when the pin is floated. Tying this pin
VCO. Connecting the pin to GND forces the VCO to a fixed
low frequency of 350kHz. Connecting the pin to INTV
CC
forces the VCO to a fixed high frequency of 535kHz. The
frequency can be programmed from 50kHz to 900kHz
by connecting a resistor from the FREQ pin to GND. The
resistor and an internal 20μA source current create a volt-
age used by the internal oscillator to set the frequency.
Alternatively, this pin can be driven with a DC voltage to
vary the frequency of the internal oscillator.
to INTV forces continuous inductor current operation.
CC
Tying this pin to a voltage greater than 1.2V and less than
INTV – 1.3V selects pulse-skipping operation. This can
CC
be done by adding a 100k resistor between the PLLIN/
MODE pin and INTV .
CC
PHASMD (Pin 2/Pin 5): This pin can be floated, tied to
SGND, ortiedtoINTV toprogramthephaserelationship
SGND (Pin 5/Pin 8): Signal Ground. All small-signal
components and compensation components should
connect to this ground, which in turn connects to PGND
at a single point.
CC
between the rising edges of BG1 and BG2, as well as the
phase relationship between BG1 and CLKOUT.
CLKOUT (Pin 3/Pin 6): A Digital Output Used for Daisy-
chainingMultipleLTC3787ICsinMultiphaseSystems.The
PHASMDpinvoltagecontrolstherelationshipbetweenBG1
RUN (Pin 6/Pin 9): Run Control Input. Forcing this pin
below 1.28V shuts down the controller. Forcing this pin
below 0.7V shuts down the entire LTC3787, reducing
quiescent current to approximately 8ꢀA. An external
and CLKOUT. This pin swings between SGND and INTV .
CC
PLLIN/MODE(Pin4/Pin7):ExternalSynchronizationInput
to Phase Detector and Forced Continuous Mode Input.
When an external clock is applied to this pin, it will force
the controller into forced continuous mode of operation
and the phase-locked loop will force the rising BG1 signal
resistor divider connected to V can set the threshold
IN
for converter operation. Once running, a 4.5ꢀA current is
sourced from the RUN pin allowing the user to program
hysteresis using the resistor values.
3787fc
9
LTC3787
PIN FUNCTIONS (QFN/SSOP)
SS (Pin 7/Pin ±0): Output Soft-Start Input. A capacitor to
ground at this pin sets the ramp rate of the output voltage
during start-up.
PGND (Pin ±9/Pin 22): Driver Power Ground. Connects
to the sources of bottom (main) N-channel MOSFETs and
the (–) terminal(s) of C and C
.
IN
OUT
–
–
SENSE2 , SENSE± (Pin 8, Pin 28/Pin ±±, Pin 3): Nega-
tive Current Sense Comparator Input. The (–) input to the
current comparator is normally connected to the negative
terminal of a current sense resistor connected in series
with the inductor.
BG2, BG± (Pin ±6, Pin 2±/Pin ±9, Pin 24): Bottom Gate.
Connect to the gate of the main N-channel MOSFET.
INTV (Pin ±7/Pin 20): Output of Internal 5.4V LDO.
CC
Power supply for control circuits and gate drivers. De-
couple this pin to GND with a minimum 4.7μF low ESR
ceramic capacitor.
+
+
SENSE2 , SENSE± (Pin 9, Pin 27/Pin ±2, Pin 2): Posi-
tive Current Sense Comparator Input. The (+) input to the
current comparator is normally connected to the positive
terminalofacurrentsenseresistor.Thecurrentsenseresis-
tor is normally placed at the input of the boost controller in
serieswiththeinductor.Thispinalsosuppliespowertothe
current comparator. The common mode voltage range on
EXTV (Pin ±8/Pin 2±): External Power Input. When this
CC
pin is between 4.8V and 6V, an internal switch bypasses
the internal regulator and supply power to INTV directly
CC
from EXTV . Do not float this pin. It can be connected to
CC
ground when not used.
+
–
VBIAS (Pin 20/Pin 23): Main Supply Pin. It is normally
SENSE and SENSE pins is 2.5V to 38V (40V abs max).
tied to the input supply V or to the output of the boost
IN
VFB (Pin ±0/Pin ±3): Error Amplifier Feedback Input. This
pin receives the remotely sensed feedback voltage from
an external resistive divider connected across the output.
converter. A bypass capacitor should be tied between this
pin and the signal ground pin. The operating voltage range
on this pin is 4.5V to 38V (40V abs max).
ITH (Pin ±±/Pin ±4): Current Control Threshold and Error
AmplifierCompensationPoint.Thevoltageonthispinsets
the current trip threshold.
PGOOD(Pin25/Pin28):PowerGoodIndicator.Open-drain
logic output that is pulled to ground when the output volt-
age is more than 10 % away from the regulated output
voltage. To avoid false trips the output voltage must be
outside the range for 25μs before this output is activated.
NC (Pin ±2/Pin ±5): No Connect.
SW2, SW± (Pin ±3, Pin 24/Pin ±6, Pin 27): Switch Node.
Connect to the source of the synchronous N-channel
MOSFET, the drain of the main N-channel MOSFET and
the inductor.
ILIM (Pin 26/Pin ±): Current Comparator Sense Voltage
Range Input. This pin is used to set the peak current
sense voltage in the current comparator. Connect this pin
to SGND, open, and INTV to set the peak current sense
CC
TG2, TG± (Pin ±4, Pin 23/Pin ±7, Pin 26): Top Gate. Con-
nect to the gate of the synchronous N-channel MOSFET.
voltage to 50mV, 75mV and 100mV, respectively.
GND (Exposed Pad Pin 29) UFD Package: Ground. Must
be soldered to the PCB for rated thermal performance.
BOOST2, BOOST± (Pin ±5, Pin 22/Pin ±8, Pin 25): Float-
ingpowersupplyforthesynchronousN-channelMOSFET.
Bypass to SW with a capacitor and supply with a Schottky
diode connected to INTV .
CC
3787fc
10
LTC3787
BLOCK DIAGRAM
INTV
CC
PHASMD
CLKOUT
DUPLICATE FOR SECOND CONTROLLER CHANNEL
S
D
BOOST
TG
B
Q
R
C
B
SHDN
SWITCHING
LOGIC
V
OUT
SW
AND
C
OUT
20ꢀA
CHARGE
PUMP
INTV
CC
FREQ
CLK2
CLK1
BG
VCO
PFD
+
–
0.425V
–
SLEEP
PGND
L
+
I
I
REV
CMP
+
+
–
+
–
–
–
2mV
SENSE
SENSE
2.8V
0.7V
PLLIN/
MODE
R
SENSE
+
SLOPE COMP
SENS LO
SYNC
DET
V
IN
C
+
IN
100k
–
2.5V
ILIM
VFB
CURRENT
LIMIT
+
–
–
1.2V
SS
EA
VBIAS
SHDN
+
–
EXTV
CC
OV
1.32V
C
C
ITH
0.5ꢀA/
4.5ꢀA
5.4V
LDO
5.4V
LDO
+
–
R
C
C
PGOOD
EN
EN
C2
+
–
1.32V
10ꢀA
SS
3.8V
11V
+
VFB
+
–
–
4.8V
INTV
SENS
LO
SGND
CC
SHDN
RUN
1.08V
C
SS
3787 BD
OPERATION
Main Control Loop
connected across the output voltage, V , to ground), to
OUT
theinternal1.200Vreferencevoltage. Inaboostconverter,
the required inductor current is determined by the load
The LTC3787 uses a constant-frequency, current mode
step-up architecture with the two controller channels
operating out of phase. During normal operation, each
external bottom MOSFET is turned on when the clock for
that channel sets the RS latch, and is turned off when the
main current comparator, ICMP, resets the RS latch. The
peak inductor current at which ICMP trips and resets the
latch is controlled by the voltage on the ITH pin, which is
the output of the error amplifier EA. The error amplifier
compares the output voltage feedback signal at the VFB
pin (which is generated with an external resistor divider
current, V and V . When the load current increases,
IN
OUT
it causes a slight decrease in VFB relative to the reference,
which causes the EA to increase the ITH voltage until the
averageinductorcurrentineachchannelmatchesthenew
requirement based on the new load current.
After the bottom MOSFET is turned off each cycle, the
top MOSFET is turned on until either the inductor current
starts to reverse, as indicated by the current comparator,
IR, or the beginning of the next clock cycle.
3787fc
11
LTC3787
OPERATION
INTV /EXTV Power
pull-up current charges this capacitor creating a voltage
ramp on the SS pin. As the SS voltage rises linearly from
CC
CC
Power for the top and bottom MOSFET drivers and most
0V to 1.2V (and beyond up to INTV ), the output voltage
CC
other internal circuitry is derived from the INTV pin.
CC
rises smoothly to its final value.
When the EXTV pin is tied to a voltage less than 4.8V,
CC
the VBIAS LDO (low dropout linear regulator) supplies
Light Load Current Operation—Burst Mode Operation,
Pulse-Skipping or Continuous Conduction
(PLLIN/MODE Pin)
5.4V from VBIAS to INTV . If EXTV is taken above
CC
CC
4.8V, the VBIAS LDO is turned off and an EXTV LDO is
CC
turned on. Once enabled, the EXTV LDO supplies 5.4V
CC
The LTC3787 can be enabled to enter high efficiency
Burst Mode operation, constant-frequency, pulse-skipping
mode or forced continuous conduction mode at low
load currents. To select Burst Mode operation, tie the
PLLIN/MODE pin to ground (e.g., SGND). To select
forced continuous operation, tie the PLLIN/MODE pin to
from EXTV to INTV . Using the EXTV pin allows the
CC
CC
CC
INTV power to be derived from an external source, thus
CC
removing the power dissipation of the VBIAS LDO.
Shutdown and Start-Up (RUN and SS Pins)
The two internal controllers of the LTC3787 can be shut
down using the RUN pin. Pulling this pin below 1.28V
shuts down the main control loops for both phases.
Pulling this pin below 0.7V disables both controllers and
most internal circuits, including the INTV LDOs. In this
state, the LTC3787 draws only 8μA of quiescent current.
INTV . To select pulse-skipping mode, tie the PLLIN/
CC
MODE pin to a DC voltage greater than 1.2V and less
than INTV – 1.3V.
CC
CC
When the controller is enabled for Burst Mode opera-
tion, the minimum peak current in the inductor is set to
approximately 30% of the maximum sense voltage even
though the voltage on the ITH pin indicates a lower value.
If the average inductor current is higher than the required
current, the error amplifier EA will decrease the voltage
on the ITH pin. When the ITH voltage drops below 0.425V,
the internal sleep signal goes high (enabling sleep mode)
and both external MOSFETs are turned off.
NOTE: Do not apply a heavy load for an extended time
while the chip is in shutdown. The top MOSFETs will be
turnedoffduringshutdownandtheoutputloadmaycause
excessive dissipation in the body diodes.
The RUN pin may be externally pulled up or driven directly
by logic. When driving the RUN pin with a low impedance
source, do not exceed the absolute maximum rating of
8V. The RUN pin has an internal 11V voltage clamp that
allows the RUN pin to be connected through a resistor to
a higher voltage (for example, V ), as long as the maxi-
mum current into the RUN pin does not exceed 100μA.
In sleep mode much of the internal circuitry is turned off
and the LTC3787 draws only 135μA of quiescent current.
In sleep mode the load current is supplied by the output
capacitor. As the output voltage decreases, the EA’s output
beginstorise. Whentheoutputvoltagedropsenough, the
sleep signal goes low and the controller resumes normal
operation by turning on the bottom external MOSFET on
the next cycle of the internal oscillator.
IN
An external resistor divider connected to V can set the
IN
threshold for converter operation. Once running, a 4.5μA
current is sourced from the RUN pin allowing the user to
program hysteresis using the resistor values.
When the controller is enabled for Burst Mode operation,
the inductor current is not allowed to reverse. The reverse
currentcomparator(IR)turnsoffthetopexternalMOSFET
just before the inductor current reaches zero, preventing
it from reversing and going negative. Thus, the controller
operates in discontinuous current operation.
The start-up of the controller’s output voltage V
is
OUT
controlled by the voltage on the SS pin. When the voltage
on the SS pin is less than the 1.2V internal reference, the
LTC3787 regulates the VFB voltage to the SS pin voltage
instead of the 1.2V reference. This allows the SS pin to
be used to program a soft-start by connecting an external
capacitor from the SS pin to SGND. An internal 10μA
3787fc
12
LTC3787
OPERATION
In forced continuous operation or when clocked by an
external clock source to use the phase-locked loop (see
theFrequencySelectionandPhase-LockedLoopsection),
the inductor current is allowed to reverse at light loads or
under large transient conditions. The peak inductor cur-
rent is determined by the voltage on the ITH pin, just as
in normal operation. In this mode, the efficiency at light
loads is lower than in Burst Mode operation. However,
continuous operation has the advantages of lower output
voltage ripple and less interference to audio circuitry, as
it maintains constant-frequency operation independent
of load current.
allows the frequency to be programmed between 50kHz
and 900kHz, as shown in Figure 6.
A phase-locked loop (PLL) is available on the LTC3787
to synchronize the internal oscillator to an external clock
source that is connected to the PLLIN/MODE pin. The
LTC3787’s phase detector adjusts the voltage (through
an internal lowpass filter) of the VCO input to align the
turn-on of the first controller’s external bottom MOSFET
to the rising edge of the synchronizing signal. Thus, the
turn-onofthesecondcontroller’sexternalbottomMOSFET
is 180 or 240 degrees out-of-phase to the rising edge of
the external clock source.
WhenthePLLIN/MODEpinisconnectedforpulse-skipping
mode,theLTC3787operatesinPWMpulse-skippingmode
at light loads. In this mode, constant-frequency operation
is maintained down to approximately 1% of designed
maximum output current. At very light loads, the current
comparator ICMP may remain tripped for several cycles
and force the external bottom MOSFET to stay off for
the same number of cycles (i.e., skipping pulses). The
inductor current is not allowed to reverse (discontinuous
operation). This mode, like forced continuous operation,
exhibits low output ripple as well as low audio noise and
reduced RF interference as compared to Burst Mode
operation. It provides higher low current efficiency than
forced continuous mode, but not nearly as high as Burst
Mode operation.
The VCO input voltage is prebiased to the operating fre-
quency set by the FREQ pin before the external clock is
applied. If prebiased near the external clock frequency,
the PLL loop only needs to make slight changes to the
VCO input in order to synchronize the rising edge of the
external clock’s to the rising edge of BG1. The ability to
prebias the loop filter allows the PLL to lock-in rapidly
without deviating far from the desired frequency.
The typical capture range of the LTC3787’s PLL is from
approximately 55kHz to 1MHz, and is guaranteed to lock
to an external clock source whose frequency is between
75kHz and 850kHz.
The typical input clock thresholds on the PLLIN/MODE
pin are 1.6V (rising) and 1.2V (falling).
Frequency Selection and Phase-Locked Loop
(FREQ and PLLIN/MODE Pins)
PolyPhase Applications (CLKOUT and PHASMD Pins)
The LTC3787 features two pins, CLKOUT and PHASMD,
that allow other controller ICs to be daisychained with
the LTC3787 in PolyPhase applications. The clock output
signal on the CLKOUT pin can be used to synchronize
additional power stages in a multiphase power supply
solution feeding a single, high current output or multiple
separate outputs. The PHASMD pin is used to adjust the
phase of the CLKOUT signal as well as the relative phases
between the two internal controllers, as summarized in
Table 1. The phases are calculated relative to the zero
degrees phase being defined as the rising edge of the
bottom gate driver output of controller 1 (BG1). Depend-
ing on the phase selection, a PolyPhase application with
Theselectionofswitchingfrequencyisatrade-offbetween
efficiency and component size. Low frequency opera-
tion increases efficiency by reducing MOSFET switching
losses, but requires larger inductance and/or capacitance
to maintain low output ripple voltage.
The switching frequency of the LTC3787’s controllers can
be selected using the FREQ pin.
If the PLLIN/MODE pin is not being driven by an external
clock source, the FREQ pin can be tied to SGND, tied to
INTV ,orprogrammedthroughanexternalresistor.Tying
CC
FREQ to SGND selects 350kHz while tying FREQ to INTV
CC
selects535kHz.PlacingaresistorbetweenFREQandSGND
3787fc
13
LTC3787
OPERATION
multiple LTC3787s can be configured for 2-, 3-, 4- , 6- and
12-phase operation.
Power Good
The PGOOD pin is connected to an open drain of an
internal N-channel MOSFET. The MOSFET turns on and
pulls the PGOOD pin low when the VFB pin voltage is not
within 10% of the 1.2V reference voltage. The PGOOD
pin is also pulled low when the corresponding RUN pin
is low (shut down). When the VFB pin voltage is within
the 10% requirement, the MOSFET is turned off and the
pin is allowed to be pulled up by an external resistor to a
source of up to 6V (abs max).
Table ±.
V
CONTROLLER 2 PHASE (°C)
CLKOUT PHASE (°C)
PHASMD
GND
180
180
240
60
90
Floating
INTV
120
CC
CLKOUT is disabled when the controller is in shutdown
or in sleep mode.
Operation When V > Regulated V
IN
OUT
Operation at Low SENSE Pin Common Mode Voltage
WhenV risesabovetheregulatedV voltage,theboost
IN
OUT
ThecurrentcomparatorintheLTC3787ispowereddirectly
controller can behave differently depending on the mode,
+
from the SENSE pin. This enables the common mode
inductor current and V voltage. In forced continuous
+
–
IN
voltage of the SENSE and SENSE pins to operate at as
lowas2.5V, whichisbelowtheUVLOthreshold. Thefigure
on the first page shows a typical application in which the
mode, the loop works to keep the top MOSFET on con-
tinuously once V rises above V . The internal charge
IN
OUT
pump delivers current to the boost capacitor to maintain
a sufficiently high TG voltage. The amount of current the
charge pump can deliver is characterized by two curves
in the Typical Performance Characteristics section.
controller’s VBIAS is powered from V
while the V
OUT
IN
+
supply can go as low as 2.5V. If the voltage on SENSE
drops below 2.5V, the SS pin will be held low. When the
SENSE voltage returns to the normal operating range, the
SS pin will be released, initiating a new soft-start cycle.
In pulse-skipping mode, if V is between 100% and
IN
110% of the regulated V
voltage, TG turns on if the
OUT
BOOST Supply Refresh and Internal Charge Pump
inductor current rises above a certain threshold and turns
off if the inductor current falls below this threshold. This
threshold current is set to approximately 6%, 4% or
3% of the maximum ILIM current when the ILIM pin is
Each top MOSFET driver is biased from the floating
bootstrap capacitor, C , which normally recharges during
B
each cycle through an external diode when the bottom
MOSFET turns on. There are two considerations for keep-
ing the BOOST supply at the required bias level. During
start-up, if the bottom MOSFET is not turned on within
100μs after UVLO goes low, the bottom MOSFET will be
forced to turn on for ~400ns. This forced refresh gener-
ates enough BOOST-SW voltage to allow the top MOSFET
ready to be fully enhanced instead of waiting for the initial
few cycles to charge up. There is also an internal charge
pump that keeps the required bias on BOOST. The charge
pump always operates in both forced continuous mode
and pulse-skipping mode. In Burst Mode operation, the
charge pump is turned off during sleep and enabled when
the chip wakes up. The internal charge pump can normally
supply a charging current of 55μA.
grounded, floating or tied to INTV , respectively. If the
CC
controller is programmed to Burst Mode operation under
this same V window, then TG remains off regardless of
IN
the inductor current.
If V rises above 110% of the regulated V
voltage in
IN
OUT
any mode, the controller turns on TG regardless of the
inductor current. In Burst Mode operation, however, the
internal charge pump turns off if the chip is asleep. With
the charge pump off, there would be nothing to prevent
the boost capacitor from discharging, resulting in an
insufficient TG voltage needed to keep the top MOSFET
completely on. To prevent excessive power dissipation
across the body diode of the top MOSFET in this situation,
the chip can be switched over to forced continuous mode
to enable the charge pump or a Schottky diode can also
be placed in parallel to the top MOSFET.
3787fc
14
LTC3787
APPLICATIONS INFORMATION
+
TheTypicalApplicationonthefirstpageisabasicLTC3787
applicationcircuit.LTC3787canbeconfiguredtouseeither
inductor DCR (DC resistance) sensing or a discrete sense
The SENSE pin also provides power to the current com-
parator. It draws ~200μA during normal operation. There
is a small base current of less than 1μA that flows into
–
–
resistor (R
) for current sensing. The choice between
SENSE
the SENSE pin. The high impedance SENSE input to the
current comparators allows accurate DCR sensing.
the two current sensing schemes is largely a design trade-
off between cost, power consumption and accuracy. DCR
sensing is becoming popular because it does not require
current sensing resistors and is more power-efficient,
especially in high current applications. However, current
sensing resistors provide the most accurate current limits
for the controller. Other external component selection is
driven by the load requirement, and begins with the se-
Filter components mutual to the sense lines should be
placed close to the LTC3787, and the sense lines should
run close together to a Kelvin connection underneath the
current sense element (shown in Figure 1). Sensing cur-
rent elsewhere can effectively add parasitic inductance
and capacitance to the current sense element, degrading
the information at the sense terminals and making the
programmed current limit unpredictable. If DCR sensing
is used (Figure 2b), sense resistor R1 should be placed
closetotheswitchingnode,topreventnoisefromcoupling
into sensitive small-signal nodes.
lection of R
(if R
is used) and inductor value.
SENSE
SENSE
Next, the power MOSFETs are selected. Finally, input and
output capacitors are selected. Note that the two control-
ler channels of the LTC3787 should be designed with the
same components.
TO SENSE FILTER,
NEXT TO THE CONTROLLER
+
–
SENSE and SENSE Pins
+
–
The SENSE and SENSE pins are the inputs to the cur-
rent comparators. The common mode input voltage range
of the current comparators is 2.5V to 38V. The current
sense resistor is normally placed at the input of the boost
controller in series with the inductor.
V
IN
INDUCTOR OR R
3787 F01
SENSE
Figure ±. Sense Lines Placement with
Inductor or Sense Resistor
VBIAS
VBIAS
V
V
IN
IN
+
+
SENSE
SENSE
(OPTIONAL)
C1
R2
DCR
L
–
–
SENSE
SENSE
INTV
INTV
CC
CC
INDUCTOR
R1
LTC3787
LTC3787
BOOST
BOOST
TG
TG
V
V
OUT
SW
BG
SW
BG
OUT
SGND
SGND
3787 F02a
3787 F02b
L
DCR
R2
R1 + R2
||
(R1 R2) • C1 =
R
= DCR •
PLACE C1 NEAR SENSE PINS
SENSE(EQ)
(2a) Using a Resistor to Sense Current
(2b) Using the Inductor DCR to Sense Current
Figure 2. Two Different Methods of Sensing Current
3787fc
15
LTC3787
APPLICATIONS INFORMATION
Sense Resistor Current Sensing
Inductor DCR Sensing
A typical sensing circuit using a discrete resistor is shown
For applications requiring the highest possible efficiency
at high load currents, the LTC3787 is capable of sensing
the voltage drop across the inductor DCR, as shown in
Figure 2b. The DCR of the inductor can be less than 1mΩ
for high current inductors. In a high current application
requiring such an inductor, conduction loss through a
sense resistor could reduce the efficiency by a few percent
compared to DCR sensing.
in Figure 2a. R
output current.
is chosen based on the required
SENSE
The current comparator has a maximum threshold
V
. When the ILIM pin is grounded, floating or
CC
SENSE(MAX)
tied to INTV , the maximum threshold is set to 50mV,
75mV or 100mV, respectively. The current comparator
threshold sets the peak of the inductor current, yielding
a maximum average inductor current, I
, equal to the
If the external R1||R2 • C1 time constant is chosen to be
exactly equal to the L/DCR time constant, the voltage drop
across the external capacitor is equal to the drop across
theinductorDCRmultipliedbyR2/(R1+R2).R2scalesthe
voltage across the sense terminals for applications where
the DCR is greater than the target sense resistor value.
To properly dimension the external filter components, the
DCR of the inductor must be known. It can be measured
using a good RLC meter, but the DCR tolerance is not
always the same and varies with temperature. Consult
the manufacturers’ data sheets for detailed information.
MAX
peak value less half the peak-to-peak ripple current, ΔI .
L
To calculate the sense resistor value, use the equation:
VSENSE(MAX)
RSENSE
=
ΔIL
IMAX
+
2
The actual value of I
required output current I
using:
for each channel depends on the
OUT(MAX)
MAX
and can be calculated
I
⎛
⎞
⎛
⎞
VOUT
OUT(MAX)
Using the inductor ripple current value from the induct-
or value calculation section, the target sense resistor
value is:
IMAX
=
•
⎜
⎟
⎜
⎟
2
V
⎝
⎠
⎝
⎠
IN
When using the controller in low V and very high voltage
IN
VSENSE(MAX)
output applications, the maximum inductor current and
correspondingly the maximum output current level will
be reduced due to the internal compensation required to
meet stability criterion for boost regulators operating at
greater than 50% duty factor. A curve is provided in the
Typical Performance Characteristics section to estimate
this reduction in peak inductor current level depending
upon the operating duty factor.
RSENSE(EQUIV)
=
ΔIL
IMAX
+
2
To ensure that the application will deliver full load current
over the full operating temperature range, choose the
minimum value for the maximum current sense threshold
(V
).
SENSE(MAX)
Next, determine the DCR of the inductor. Where provided,
use the manufacturer’s maximum value, usually given at
20°C. Increase this value to account for the temperature
coefficient of resistance, which is approximately 0.4%/°C.
Aconservativevalueforthemaximuminductortemperature
(T
) is 100°C.
L(MAX)
3787fc
16
LTC3787
APPLICATIONS INFORMATION
To scale the maximum inductor DCR to the desired sense
resistor value, use the divider ratio:
Inductor Value Calculation
The operating frequency and inductor selection are in-
terrelated in that higher operating frequencies allow the
use of smaller inductor and capacitor values. Why would
anyone ever choose to operate at lower frequencies with
larger components? The answer is efficiency. A higher
frequency generally results in lower efficiency because
of MOSFET gate charge and switching losses. Also, at
higher frequency the duty cycle of body diode conduction
is higher, which results in lower efficiency. In addition to
this basic trade-off, the effect of inductor value on ripple
currentandlowcurrentoperationmustalsobeconsidered.
RSENSE(EQUIV)
RD =
DCRMAX at TL(MAX)
C1 is usually selected to be in the range of 0.1μF to 0.47μF.
ThisforcesR1||R2toaround2k, reducingerrorthatmight
have been caused by the SENSE pin’s 1μA current.
–
The equivalent resistance R1|| R2 is scaled to the room
temperature inductance and maximum DCR:
L
R1||R2 =
(DCR at 20°C)•C1
The inductor value has a direct effect on ripple current.
The inductor ripple current ΔI decreases with higher
L
The sense resistor values are:
inductance or frequency and increases with higher V :
IN
R1•RD
1−RD
R1||R2
RD
⎛
⎞
R1=
; R2 =
V
f •L
V
IN
VOUT
IN
ΔIL =
1−
⎜
⎟
⎝
⎠
The maximum power loss in R1 is related to duty cycle,
and will occur in continuous mode at V = 1/2V
Accepting larger values of ΔI allows the use of low
L
:
IN
OUT
inductances, but results in higher output voltage ripple
(VOUT − V )• V
IN
IN
and greater core losses. A reasonable starting point for
P
=
LOSS_R1
R1
setting ripple current is ΔI = 0.3(I
ΔI occurs at V = 1/2V .
). The maximum
MAX
L
L
IN
OUT
Ensure that R1 has a power rating higher than this value.
If high efficiency is necessary at light loads, consider this
power loss when deciding whether to use DCR sensing or
sense resistors. Light load power loss can be modestly
higher with a DCR network than with a sense resistor, due
totheextraswitchinglossesincurredthroughR1.However,
DCR sensing eliminates a sense resistor, reduces conduc-
tion losses and provides higher efficiency at heavy loads.
Peak efficiency is about the same with either method.
The inductor value also has secondary effects. The tran-
sition to Burst Mode operation begins when the average
inductor current required results in a peak current below
25% of the current limit determined by R
inductor values (higher ΔI ) will cause this to occur at
lower load currents, which can cause a dip in efficiency in
the upper range of low current operation. In Burst Mode
operation, lower inductance values will cause the burst
frequency to decrease. Once the value of L is known, an
inductor with low DCR and low core losses should be
selected.
. Lower
SENSE
L
3787fc
17
LTC3787
APPLICATIONS INFORMATION
Power MOSFET Selection
power dissipations in each channel at maximum output
current are given by:
Two external power MOSFETs must be selected for each
controller in the LTC3787: one N-channel MOSFET for the
bottom (main) switch, and one N-channel MOSFET for the
top (synchronous) switch.
2
I
⎛
⎞
(VOUT − V )VOUT
OUT(MAX)
IN
V2
PMAIN
=
•
• 1+ δ
(
)
⎜
⎟
2
⎝
⎠
IN
IOUT(MAX)
• RDS(ON) +k • V3
•
The peak-to-peak gate drive levels are set by the INTV
voltage. This voltage is typically 5.4V during start-up
CC
OUT
2• V
IN
(see EXTV pin connection). Consequently, logic-level
threshold MOSFETs must be used in most applications.
CC
• CMILLER • f
2
Pay close attention to the BV
MOSFETs as well; many of the logic level MOSFETs are
limited to 30V or less.
specification for the
DSS
I
⎛
⎞
V
VOUT
OUT(MAX)
IN
PSYNC
=
•
• 1+ δ •R
DS(ON)
(
)
⎜
⎟
2
⎝
⎠
where δ is the temperature dependency of R
(ap-
DS(ON)
Selection criteria for the power MOSFETs include the
proximately 1Ω) is the effective driver resistance at the
MOSFET’s Miller threshold voltage. The constant k, which
accounts for the loss caused by reverse recovery current,
is inversely proportional to the gate drive current and has
an empirical value of 1.7.
on-resistance R
, Miller capacitance C , input
DS(ON) MILLER
voltage and maximum output current. Miller capacitance,
, can be approximated from the gate charge curve
C
MILLER
usually provided on the MOSFET manufacturer’s data
sheet. C is equal to the increase in gate charge
MILLER
2
BothMOSFETshaveI RlosseswhilethebottomN-channel
along the horizontal axis while the curve is approximately
flat divided by the specified change in VDS. This result
is then multiplied by the ratio of the application applied
VDS to the gate charge curve specified VDS. When the IC
is operating in continuous mode, the duty cycles for the
top and bottom MOSFETs are given by:
equation includes an additional term for transition losses,
which are highest at low input voltages. For high V the
IN
high current efficiency generally improves with larger
MOSFETs, while for low V the transition losses rapidly
IN
increasetothepointthattheuseofahigherR
device
DS(ON)
withlowerC
actuallyprovideshigherefficiency.The
MILLER
VOUT − V
synchronous MOSFET losses are greatest at high input
voltage when the bottom switch duty factor is low or dur-
ing overvoltage when the synchronous switch is on close
to 100% of the period.
IN
Main Switch Duty Cycle =
VOUT
V
VOUT
IN
Synchronous SwitchDuty Cycle=
The term (1+ δ) is generally given for a MOSFET in the
IfthemaximumoutputcurrentisI
andeachchan-
OUT(MAX)
form of a normalized R
vs Temperature curve, but
DS(ON)
nel takes one half of the total output current, the MOSFET
δ = 0.005/°C can be used as an approximation for low
voltage MOSFETs.
3787fc
18
LTC3787
APPLICATIONS INFORMATION
C and C
Selection
squarewave,theripplecurrentrequirementsfortheoutput
capacitor depend on the duty cycle, the number of phases
and the maximum output current. Figure 3 illustrates the
normalized output capacitor ripple current as a function of
duty cycle in a 2-phase configuration. To choose a ripple
current rating for the output capacitor, first establish the
duty cycle range based on the output voltage and range
of input voltage. Referring to Figure 3, choose the worst-
case high normalized ripple current as a percentage of the
maximum load current.
IN
OUT
The input ripple current in a boost converter is relatively
low(comparedwiththeoutputripplecurrent),becausethis
currentiscontinuous.TheinputcapacitorC voltagerating
IN
should comfortably exceed the maximum input voltage.
Although ceramic capacitors can be relatively tolerant of
overvoltage conditions, aluminum electrolytic capacitors
are not. Be sure to characterize the input voltage for any
possible overvoltage transients that could apply excess
stress to the input capacitors.
Multiple capacitors placed in parallel may be needed to
meet the ESR and RMS current handling requirements.
Dry tantalum, special polymer, aluminum electrolytic and
ceramic capacitors are all available in surface mount
packages. Ceramic capacitors have excellent low ESR
characteristics but can have a high voltage coefficient.
Capacitors are now available with low ESR and high ripple
current ratings (e.g., OS-CON and POSCAP).
ThevalueofC isafunctionofthesourceimpedance, and
IN
ingeneral,thehigherthesourceimpedance,thehigherthe
required input capacitance. The required amount of input
capacitance is also greatly affected by the duty cycle. High
output current applications that also experience high duty
cycles can place great demands on the input supply, both
in terms of DC current and ripple current.
Inaboostconverter,theoutputhasadiscontinuouscurrent,
so C
must be capable of reducing the output voltage
3.25
3.00
2.75
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0
OUT
ripple.TheeffectsofESR(equivalentseriesresistance)and
the bulk capacitance must be considered when choosing
the right capacitor for a given output ripple voltage. The
steady ripple voltage due to charging and discharging
the bulk capacitance in a single phase boost converter
is given by:
1-PHASE
IOUT(MAX) •(VOUT − V
)
IN(MIN)
2-PHASE
VRIPPLE
=
V
COUT • VOUT • f
0.4 0.5
DUTY CYCLE OR (1-V /V
0.1 0.2 0.3
0.6 0.7 0.8 0.9
)
IN OUT
where C
is the output filter capacitor.
3787 F03
OUT
Figure 3. Normalized Output Capacitor Ripple
Current (RMS) for a Boost Converter
The steady ripple due to the voltage drop across the ESR
is given by:
ΔV
= I
• ESR
ESR
L(MAX)
PolyPhase Operation
The LTC3787 is configured as a 2-phase single output
converter where the outputs of the two channels are
connected together and both channels have the same
duty cycle. With 2-phase operation, the two channels
are operated 180 degrees out-of-phase. This effectively
interleaves the output capacitor current pulses, greatly
reducing the output capacitor ripple current. As a result,
the ESR requirement of the capacitor can be relaxed.
Because the ripple current in the output capacitor is a
For output loads that demand high current, multiple
LTC3787s can be cascaded to run out-of-phase to provide
more output current and at the same time to reduce input
and output voltage ripple. The PLLIN/MODE pin allows the
LTC3787 to synchronize to the CLKOUT signal of another
LTC3787. The CLKOUT signal can be connected to the
PLLIN/MODE pin of the following LTC3787 stage to line
up both the frequency and the phase of the entire system.
3787fc
19
LTC3787
APPLICATIONS INFORMATION
Tying the PHASMD pin to INTV , SGND or floating
or 180°. Figure 4 shows the connections necessary for
3-, 4-, 6- or 12-phase operation. A total of 12 phases can
be cascaded to run simultaneously out-of-phase with
respect to each other.
CC
generates a phase difference (between PLLIN/MODE
and CLKOUT) of 240°, 60° or 90°, respectively, and a
phase difference (between CH1 and CH2) of 120°, 180°
0,240
120, CHANNEL 2 NOT USED
PLLIN/MODE CLKOUT
+120
V
PLLIN/MODE CLKOUT
OUT
PHASMD
LTC3787
SS
PHASMD
LTC3787
SS
RUN
ITH
RUN
ITH
VFB
VFB
INTV
CC
(4a) 3-Phase Operation
0,180
PLLIN/MODE CLKOUT
90,270
PLLIN/MODE CLKOUT
+90
V
OUT
PHASMD
LTC3787
SS
PHASMD
LTC3787
SS
RUN
ITH
RUN
ITH
VFB
VFB
(4b) 4-Phase Operation
0,180
PLLIN/MODE CLKOUT
60,240
120,300
+60
+60
V
OUT
PLLIN/MODE CLKOUT
PLLIN/MODE CLKOUT
PHASMD
LTC3787
SS
PHASMD
LTC3787
SS
PHASMD
LTC3787
SS
RUN
ITH
RUN
ITH
RUN
ITH
VFB
VFB
VFB
(4c) 6-Phase Operation
0,180
PLLIN/MODE CLKOUT
60,240
+60
PLLIN/MODE CLKOUT
120,300
+60
+90
V
OUT
PLLIN/MODE CLKOUT
PHASMD
LTC3787
SS
PHASMD
LTC3787
SS
PHASMD
LTC3787
SS
RUN
ITH
RUN
ITH
RUN
ITH
VFB
VFB
VFB
210,30
PLLIN/MODE CLKOUT
270,90
PLLIN/MODE CLKOUT
330,150
PLLIN/MODE CLKOUT
+60
+60
PHASMD
LTC3787
SS
PHASMD
LTC3787
SS
PHASMD
LTC3787
SS
RUN
ITH
RUN
ITH
RUN
ITH
VFB
VFB
VFB
3787 F04
(4d) ±2-Phase Operation
Figure 4. PolyPhase Operation
3787fc
20
LTC3787
APPLICATIONS INFORMATION
Setting Output Voltage
INTV Regulators
CC
The LTC3787 output voltage is set by an external feedback
resistordividercarefullyplacedacrosstheoutput,asshown
in Figure 5. The regulated output voltage is determined by:
The LTC3787 features two separate internal P-channel
low dropout linear regulators (LDO) that supply power at
the INTV pin from either the VBIAS supply pin or the
CC
EXTV pin depending on the connection of the EXTV
CC
CC
⎛
⎞
RB
RA
pin. INTV powers the gate drivers and much of the
VOUT =1.2V 1+
CC
⎜
⎝
⎟
⎠
LTC3787’s internal circuitry. The VBIAS LDO and the
EXTV LDO regulate INTV to 5.4V. Each of these can
CC
CC
Great care should be taken to route the VFB line away
from noise sources, such as the inductor or the SW line.
Also keep the VFB node as small as possible to avoid
noise pickup.
supplyatleast50mAandmustbebypassedtogroundwith
a minimum of 4.7μF ceramic capacitor. Good bypassing
is needed to supply the high transient currents required
by the MOSFET gate drivers and to prevent interaction
between the channels.
V
OUT
High input voltage applications in which large MOSFETs
are being driven at high frequencies may cause the maxi-
mum junction temperature rating for the LTC3787 to be
R
B
LTC3787
VFB
R
A
exceeded. The INTV current, which is dominated by the
CC
3787 F05
gate charge current, may be supplied by either the VBIAS
LDO or the EXTV LDO. When the voltage on the EXTV
CC
CC
Figure 5. Setting Output Voltage
pin is less than 4.8V, the VBIAS LDO is enabled. In this
case, power dissipation for the IC is highest and is equal
Soft-Start (SS Pin)
The start-up of V
to VBIAS • I
. The gate charge current is dependent
INTVCC
is controlled by the voltage on the
OUT
on operating frequency, as discussed in the Efficiency
Considerations section. The junction temperature can be
estimated by using the equations given in Note 3 of the
Electrical Characteristics. For example, at 70°C ambient
SS pin. When the voltage on the SS pin is less than the
internal 1.2V reference, the LTC3787 regulates the VFB
pin voltage to the voltage on the SS pin instead of 1.2V.
temperature, theLTC3787INTV currentislimitedtoless
CC
Soft-startisenabledbysimplyconnectingacapacitorfrom
the SS pin to ground, as shown in Figure 6. An internal
10μA current source charges the capacitor, providing a
linear ramping voltage at the SS pin. The LTC3787 will
than 32mA in the QFN package from a 40V VBIAS supply
when not using the EXTV supply:
CC
T = 70°C + (32mA)(40V)(43°C/W) = 125°C
J
regulate the VFB pin (and hence, V ) according to the
OUT
In an SSOP package, the INTV current is limited to
CC
voltage on the SS pin, allowing V
to rise smoothly
OUT
less than 15mA from a 40V supply when not using the
from V to its final regulated value. The total soft-start
IN
EXTV supply:
CC
time will be approximately:
T = 70°C + (15mA)(40V)(90°C/W) = 125°C
J
1.2V
10µA
tSS =CSS
•
To prevent the maximum junction temperature from being
exceeded, the input supply current must be checked while
operating in continuous conduction mode (PLLIN/MODE
LTC3787
SS
= INTV ) at maximum V .
CC
IN
C
SS
When the voltage applied to EXTV rises above 4.8V, the
SGND
CC
3787 F06
V LDO is turned off and the EXTV LDO is enabled. The
IN
CC
EXTV LDO remains on as long as the voltage applied to
CC
Figure 6. Using the SS Pin to Program Soft-Start
3787fc
21
LTC3787
APPLICATIONS INFORMATION
EXTV remains above 4.55V. The EXTV LDO attempts
output voltage: V
= V
+ V
. The value of
INTVCC
CC
CC
BOOST
OUT
to regulate the INTV voltage to 5.4V, so while EXTV
the boost capacitor C needs to be 100 times that of the
CC
CC
CC
CC
B
is less than 5.4V, the LDO is in dropout and the INTV
total input capacitance of the topside MOSFET(s). The
voltage is approximately equal to EXTV . When EXTV
reverse breakdown of the external Schottky diode must
CC
is greater than 5.4V, up to an absolute maximum of 6V,
be greater than V
.
OUT(MAX)
INTV is regulated to 5.4V.
CC
The external diode D can be a Schottky diode or silicon
B
Significant thermal gains can be realized by powering
diode,butineithercaseitshouldhavelowleakageandfast
recovery. Paycloseattentiontothereverseleakageathigh
temperatures where it generally increases substantially.
INTV from an external supply. Tying the EXTV pin
CC
CC
to a 5V supply reduces the junction temperature in the
previous example from 125°C to 79°C in a QFN package:
Each of the topside MOSFET drivers includes an internal
chargepumpthatdeliverscurrenttothebootstrapcapaci-
tor from the BOOST pin. This charge current maintains
the bias voltage required to keep the top MOSFET on
continuously during dropout/overvoltage conditions. The
Schottky/silicon diodes selected for the topside drivers
shouldhaveareverseleakagelessthantheavailableoutput
current the charge pump can supply. Curves displaying
the available charge pump current under different operat-
ing conditions can be found in the Typical Performance
Characteristics section.
T = 70°C + (32mA)(5V)(43°C/W) = 77°C
J
and from 125°C to 74°C in an SSOP package:
T = 70°C + (15mA)(5V)(90°C/W) = 77°C
J
If more current is required through the EXTV LDO than
CC
is specified, an external Schottky diode can be added be-
tween the EXTV and INTV pins. Make sure that in all
CC
CC
cases EXTV ≤ VBIAS (even at start-up and shutdown).
CC
The following list summarizes possible connections for
EXTV :
CC
A leaky diode D in the boost converter can not only
B
EXTV Grounded.ThiswillcauseINTV tobepowered
CC
CC
prevent the top MOSFET from fully turning on but it can
fromtheinternal5.4Vregulatorresultinginanefficiency
also completely discharge the bootstrap capacitor C and
B
penalty at high input voltages.
create a current path from the input voltage to the BOOST
pin to INTV . This can cause INTV to rise if the diode
EXTV Connected to an External Supply. If an external
CC
CC
CC
leakage exceeds the current consumption on INTV .
supply is available in the 5V to 6V range, it may be used
CC
This is particularly a concern in Burst Mode operation
to provide power. Ensure that EXTV is always lower
CC
where the load on INTV can be very small. The external
than VBIAS.
CC
Schottky or silicon diode should be carefully chosen such
Topside MOSFET Driver Supply (C , D )
that INTV never gets charged up much higher than its
B
B
CC
normal regulation voltage.
ExternalbootstrapcapacitorsC connectedtotheBOOST
B
pins supply the gate drive voltages for the topside
Fault Conditions: Overtemperature Protection
MOSFETs. Capacitor C in the Block Diagram is charged
B
At higher temperatures, or in cases where the internal
power dissipation causes excessive self heating on-chip
though external diode D from INTV when the SW pin
B
CC
is low. When one of the topside MOSFETs is to be turned
(such as an INTV short to ground), the overtemperature
on, the driver places the C voltage across the gate and
CC
B
shutdown circuitry will shut down the LTC3787. When the
sourceofthedesiredMOSFET.ThisenhancestheMOSFET
junction temperature exceeds approximately 170°C, the
and turns on the topside switch. The switch node volt-
overtemperaturecircuitrydisablestheINTV LDO,causing
age, SW, rises to V
and the BOOST pin follows. With
CC
OUT
the INTV supply to collapse and effectively shut down
the topside MOSFET on, the boost voltage is above the
CC
3787fc
22
LTC3787
APPLICATIONS INFORMATION
the entire LTC3787 chip. Once the junction temperature
input. When the external clock frequency is less than f
,
OSC
dropsbacktoapproximately155°C, theINTV LDOturns
current is sunk continuously, pulling down the VCO input.
If the external and internal frequencies are the same but
exhibit a phase difference, the current sources turn on for
an amount of time corresponding to the phase difference.
The voltage at the VCO input is adjusted until the phase
and frequency of the internal and external oscillators are
identical. At the stable operating point, the phase detector
output is high impedance and the internal filter capacitor,
CC
back on. Long term overstress (T > 125°C) should be
J
avoided as it can degrade the performance or shorten
the life of the part.
Since the shutdown may occur at full load, beware that
the load current will result in high power dissipation in
the body diodes of the top MOSFETs. In this case, PGOOD
output may be used to turn the system load off.
C
, holds the voltage at the VCO input.
LP
Phase-Locked Loop and Frequency Synchronization
Typically,theexternalclock(onthePLLIN/MODEpin)input
highthresholdis1.6V,whiletheinputlowthresholdis1.2V.
The LTC3787 has an internal phase-locked loop (PLL)
comprised of a phase frequency detector, a lowpass filter
and a voltage-controlled oscillator (VCO). This allows the
turn-on of the bottom MOSFET of channel 1 to be locked
to the rising edge of an external clock signal applied to
the PLLIN/MODE pin. The turn-on of channel 2’s bot-
tom MOSFET is thus 180 degrees out-of-phase with the
external clock. The phase detector is an edge-sensitive
digitaltypethatprovideszerodegreesphaseshiftbetween
the external and internal oscillators. This type of phase
detector does not exhibit false lock to harmonics of the
external clock.
Note that the LTC3787 can only be synchronized to an
external clock whose frequency is within range of the
LTC3787’s internal VCO, which is nominally 55kHz to
1MHz.Thisisguaranteedtobebetween75kHzand850kHz.
RapidphaselockingcanbeachievedbyusingtheFREQpin
to set a free-running frequency near the desired synchro-
nization frequency. The VCO’s input voltage is prebiased
at a frequency corresponding to the frequency set by the
FREQ pin. Once prebiased, the PLL only needs to adjust
the frequency slightly to achieve phase lock and synchro-
nization. Although it is not required that the free-running
frequency be near external clock frequency, doing so will
prevent the operating frequency from passing through a
large range of frequencies as the PLL locks.
If the external clock frequency is greater than the internal
oscillator’sfrequency,f ,thencurrentissourcedcontinu-
OSC
ously from the phase detector output, pulling up the VCO
1000
900
800
700
600
500
400
300
200
100
0
15 25 35 45 55 65 75 85 95 105 115 125
FREQ PIN RESISTOR (k)
3787 F07
Figure 7. Relationship Between Oscillator
Frequency and Resistor Value at the FREQ Pin
3787fc
23
LTC3787
APPLICATIONS INFORMATION
Table 2 summarizes the different states in which the FREQ
pin can be used.
2
INTV regulator current, 3) I R losses, 4) bottom MOS-
CC
FET transition losses, 5) body diode conduction losses.
1. The VBIAS current is the DC supply current given in the
ElectricalCharacteristicstable,whichexcludesMOSFET
driver and control currents. VBIAS current typically
results in a small (<0.1%) loss.
Table 2.
FREQ PIN
PLLIN/MODE PIN
DC Voltage
FREQUENCY
350kHz
0V
INTV
DC Voltage
535kHz
CC
Resistor
DC Voltage
50kHz to 900kHz
2. INTV current is the sum of the MOSFET driver and
CC
Any of the Above
External Clock
Phase Locked to
External Clock
control currents. The MOSFET driver current results
from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched from
low to high to low again, a packet of charge, dQ, moves
Minimum On-Time Considerations
Minimum on-time, t , is the smallest time duration
that the LTC3787 is capable of turning on the bottom
MOSFET. It is determined by internal timing delays and
the gate charge required to turn on the top MOSFET. Low
duty cycle applications may approach this minimum on-
time limit.
from INTV to ground. The resulting dQ/dt is a current
CC
ON(MIN)
out of INTV that is typically much larger than the
CC
control circuit current. In continuous mode, I
GATECHG
= f(Q + Q ), where Q and Q are the gate charges of
T
B
T
B
the topside and bottom side MOSFETs.
2
3. DC I R losses. These arise from the resistances of the
MOSFETs,sensingresistor,inductorandPCboardtraces
andcausetheefficiencytodropathighoutputcurrents.
In forced continuous mode, if the duty cycle falls below
what can be accommodated by the minimum on-time,
the controller will begin to skip cycles but the output will
continuetoberegulated.Morecycleswillbeskippedwhen
4. Transition losses apply only to the bottom MOSFET(s),
and become significant only when operating at low
inputvoltages.Transitionlossescanbeestimatedfrom:
V increases. Once V rises above V , the loop keeps
IN
IN
OUT
the top MOSFET continuously on. The minimum on-time
for the LTC3787 is approximately 110ns.
3
I
VOUT
Transition Loss =(1.7)
•
OUT(MAX) •CRSS •f
2
V
IN
Efficiency Considerations
5. Body diode conduction losses are more significant at
higherswitchingfrequency. Duringthedeadtime, theloss
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the greatest improvement. Percent efficiency
can be expressed as:
in the top MOSFETs is I
• V , where V is around
OUT
DS DS
0.7V. At higher switching frequency, the dead time be-
comes a good percentage of switching cycle and causes
the efficiency to drop.
Other hidden losses, such as copper trace and internal
batteryresistances,canaccountforanadditionalefficiency
degradation in portable systems. It is very important to
includethesesystem-levellossesduringthedesignphase.
%Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc., are the individual losses as a percent-
age of input power.
Although all dissipative elements in the circuit produce
losses, five main sources usually account for most of
the losses in LTC3787 circuits: 1) IC VBIAS current, 2)
3787fc
24
LTC3787
APPLICATIONS INFORMATION
Checking Transient Response
is why it is better to look at the ITH pin signal which is
in the feedback loop and is the filtered and compensated
control loop response.
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
The gain of the loop will be increased by increasing R
C
and the bandwidth of the loop will be increased by de-
load current. When a load step occurs, V
shifts by an
OUT
creasing C . If RC is increased by the same factor that C
amount equal to ΔI
, where ESR is the effective
C
C
LOAD(ESR)
is decreased, the zero frequency will be kept the same,
thereby keeping the phase shift the same in the most
critical frequency range of the feedback loop. The output
voltage settling behavior is related to the stability of the
closed-loopsystemandwilldemonstratetheactualoverall
supply performance.
series resistance of C . ΔI
also begins to charge or
OUT
LOAD
discharge C
generating the feedback error signal that
OUT
forces the regulator to adapt to the current change and
return V
time V
to its steady-state value. During this recovery
can be monitored for excessive overshoot or
OUT
OUT
ringing, which would indicate a stability problem. OPTI-
LOOP compensation allows the transient response to be
optimized over a wide range of output capacitance and
ESR values. The availability of the ITH pin not only allows
optimization of control loop behavior, but it also provides
a DC coupled and AC filtered closed loop response test
point. The DC step, rise time and settling at this test
point truly reflects the closed loop response. Assuming a
predominantly second order system, phase margin and/
or damping factor can be estimated using the percentage
of overshoot seen at this pin. The bandwidth can also be
estimated by examining the rise time at the pin. The ITH
external components shown in the Figure 10 circuit will
provide an adequate starting point for most applications.
A second, more severe transient is caused by switching
in loads with large (>1μF) supply bypass capacitors. The
dischargedbypasscapacitorsareeffectivelyputinparallel
with C
, causing a rapid drop in V
. No regulator can
OUT
OUT
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If the ratio of
C
to C
is greater than 1:50, the switch rise time
LOAD
OUT
should be controlled so that the load rise time is limited to
approximately 25 • C . Thus, a 10μF capacitor would
LOAD
require a 250μs rise time, limiting the charging current
to about 200mA.
Design Example
The ITH series R -C filter sets the dominant pole-zero
C
C
loop compensation. The values can be modified slightly
to optimize transient response once the final PC layout
is complete and the particular output capacitor type and
value have been determined. The output capacitors must
beselectedbecausethevarioustypesandvaluesdetermine
the loop gain and phase. An output current pulse of 20%
to 80% of full-load current having a rise time of 1μs to
10μs will produce output voltage and ITH pin waveforms
that will give a sense of the overall loop stability without
breaking the feedback loop.
As a design example, assume V = 12V (nominal),
IN
V
IN
= 22V(max),V =24V,I
=8A,V
=
OUT
OUT(MAX)
SENSE(MAX)
75mV, and f = 350kHz.
The components are designed based on single channel
operation. The inductance value is chosen first based on
a 30% ripple current assumption. Tie the PLLIN/MODE
pin to GND, generating 350kHz operation. The minimum
inductance for 30% ripple current is:
⎛
⎞
V
f •L
V
IN
VOUT
IN
ΔIL =
1−
⎜
⎟
Placing a power MOSFET and load resistor directly across
the output capacitor and driving the gate with an ap-
propriate signal generator is a practical way to produce
a realistic load step condition. The initial output voltage
step resulting from the step change in output current may
not be within the bandwidth of the feedback loop, so this
signal cannot be used to determine phase margin. This
⎝
⎠
The largest ripple happens when V = 1/2V
= 12V,
OUT
IN
where the average maximum inductor current for each
channel is:
I
⎛
⎞
⎛
⎞
VOUT
OUT(MAX)
IMAX
=
•
= 8A
⎜
⎟
⎜
⎟
2
V
⎝
⎠
⎝
⎠
IN
3787fc
25
LTC3787
APPLICATIONS INFORMATION
A 6.8μH inductor will produce a 31% ripple current. The
peak inductor current will be the maximum DC value plus
one half the ripple current, or 9.25A.
2. Are the signal and power grounds kept separate? The
combined IC signal ground pin and the ground return of
C
mustreturntothecombinedC (–)terminals.
INTVCC
OUT
The path formed by the bottom N-channel MOSFET
and the capacitor should have short leads and PC trace
lengths. The output capacitor (–) terminals should be
connected as close as possible to the source terminals
of the bottom MOSFETs.
The R
resistor value can be calculated by using the
SENSE
maximum current sense voltage specification with some
accommodation for tolerances:
75mV
9.25A
RSENSE
≤
= 0.008Ω
3. Does the LTC3787 VFB pin’s resistive divider connect to
Choosing 1% resistors: R = 5k and R = 95.3k yields an
output voltage of 24.072V.
the (+) terminal of C ? The resistive divider must be
A
B
OUT
connected between the (+) terminal of C
and signal
OUT
ground and placed close to the VFB pin. The feedback
resistor connections should not be along the high cur-
rent input feeds from the input capacitor(s).
ThepowerdissipationonthetopsideMOSFETineachchan-
nel can be easily estimated. Choosing a Vishay Si7848BDP
MOSFET results in: R
= 0.012Ω, C
= 150pF.
DS(ON)
MILLER
–
+
At maximum input voltage with T (estimated) = 50°C:
4. Are the SENSE and SENSE leads routed together with
minimumPCtracespacing?Thefiltercapacitorbetween
(24V –12V) 24V
PMAIN
=
•(4A)2
+
–
SENSE and SENSE should be as close as possible
to the IC. Ensure accurate current sensing with Kelvin
connections at the sense resistor.
(12V)2
• 1+(0.005)(50°C – 25°C) •0.008Ω
⎡
⎤
⎣
⎦
4A
12V
+ (1.7)(24V)3
(150pF)(350kHz)= 0.7W
5. Is the INTV decoupling capacitor connected close
CC
to the IC, between the INTV and the power ground
CC
C
is chosen to filter the square current in the output.
The maximum output current peak is:
pins? This capacitor carries the MOSFET drivers’ cur-
rent peaks. An additional 1μF ceramic capacitor placed
OUT
immediatelynexttotheINTV andPGNDpinscanhelp
improve noise performance substantially.
CC
31%
2
⎛
⎝
⎞
IOUT(PEAK) = 8 • 1+
= 9.3A
⎜
⎟
⎠
6. Keep the switching nodes (SW1, SW2), top gate nodes
(TG1, TG2) and boost nodes (BOOST1, BOOST2) away
from sensitive small-signal nodes, especially from
the opposites channel’s voltage and current sensing
feedback pins. All of these nodes have very large and
fast moving signals and, therefore, should be kept on
the output side of the LTC3787 and occupy a minimal
PC trace area.
A low ESR (5mΩ) capacitor is suggested. This capacitor
will limit output voltage ripple to 46.5mV (assuming ESR
dominate ripple).
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the IC. These items are also illustrated graphically in the
layout diagram of Figure 8. Figure 9 illustrates the current
waveforms present in the various branches of the 2-phase
synchronousregulatorsoperatinginthecontinuousmode.
Check the following in your layout:
7. Use a modified “star ground” technique: a low imped-
ance, large copper area central grounding point on
the same side of the PC board as the input and output
capacitors with tie-ins for the bottom of the INTV
CC
decouplingcapacitor,thebottomofthevoltagefeedback
resistive divider and the SGND pin of the IC.
1.PutthebottomN-channelMOSFETsMBOT1andMBOT2
and the top N-channel MOSFETs MTOP1 and MTOP2
in one compact area with C
.
OUT
3787fc
26
LTC3787
APPLICATIONS INFORMATION
–
SENSE1
ILIM
PGOOD
SW1
+
SENSE1
V
PULL-UP
R
L1
SENSE1
TG1
LTC3787
C
B1
PHSMD
CLKOUT
FREQ
PLLIN/MODE
BOOST1
BG1
M1
+
M2
f
IN
VBIAS
PGND
GND
V
V
SGND
RUN
VFB
IN
EXTV
CC
INTV
CC
ITH
BG2
M3
+
C
B2
M4
BOOST2
OUT
R
SS
L2
SENSE2
TG2
SW2
+
SENSE2
–
SENSE2
3787 F08
Figure 8. Recommended Printed Circuit Layout Diagram
L1
R
SENSE1
SW1
V
V
OUT
IN
R
IN
C
IN
C
OUT
R
L
L2
R
SENSE2
BOLD LINES INDICATE
HIGH SWITCHING
SW2
CURRENT. KEEP LINES
TO A MINIMUM LENGTH.
3787 F09
Figure 9. Branch Current Waveforms
3787fc
27
LTC3787
APPLICATIONS INFORMATION
PC Board Layout Debugging
Reduce V from its nominal level to verify operation with
IN
high duty cycle. Check the operation of the undervoltage
Start with one controller on at a time. It is helpful to use
a DC-50MHz current probe to monitor the current in the
inductor while testing the circuit. Monitor the output
switching node (SW pin) to synchronize the oscilloscope
to the internal oscillator and probe the actual output volt-
age. Check for proper performance over the operating
voltage and current range expected in the application.
The frequency of operation should be maintained over the
input voltage range down to dropout and until the output
load drops below the low current operation threshold—
typically 10% of the maximum designed current level in
Burst Mode operation.
lockout circuit by further lowering V while monitoring
IN
the outputs to verify operation.
Investigate whether any problems exist only at higher out-
put currents or only at higher input voltages. If problems
coincide with high input voltages and low output currents,
look for capacitive coupling between the BOOST, SW, TG,
and possibly BG connections and the sensitive voltage
and current pins. The capacitor placed across the current
sensing pins needs to be placed immediately adjacent to
the pins of the IC. This capacitor helps to minimize the
effects of differential noise injection due to high frequency
capacitive coupling.
Thedutycyclepercentageshouldbemaintainedfromcycle
tocycleinawelldesigned, lownoisePCBimplementation.
Variation in the duty cycle at a subharmonic rate can sug-
gest noise pickup at the current or voltage sensing inputs
or inadequate loop compensation. Overcompensation of
the loop can be used to tame a poor PC layout if regulator
bandwidth optimization is not required. Only after each
controllerischeckedforitsindividualperformanceshould
both controllers be turned on at the same time. A particu-
larly difficult region of operation is when one controller
channel is nearing its current comparator trip point while
the other channel is turning on its bottom MOSFET. This
occurs around the 50% duty cycle on either channel due
to the phasing of the internal clocks and may cause minor
duty cycle jitter.
An embarrassing problem which can be missed in an oth-
erwiseproperlyworkingswitchingregulator, resultswhen
the current sensing leads are hooked up backwards. The
output voltage under this improper hook-up will still be
maintained, but the advantages of current mode control
will not be realized. Compensation of the voltage loop will
be much more sensitive to component selection. This
behavior can be investigated by temporarily shorting out
the current sensing resistor—don’t worry, the regulator
will still maintain control of the output voltage.
3787fc
28
LTC3787
TYPICAL APPLICATIONS
–
SENSE1
100k
+
+
C
SENSE1
PGOOD
TG1
INTV
CC
OUTA1
C
OUTB1
220ꢀF
L1
3.3ꢀH
R
22ꢀF
SENSE1
4mΩ
MTOP1
MBOT1
ILIM
s 4
PHASMD
CLKOUT
SW1
C
, 0.1ꢀF
B1
PLLIN/MODE BOOST1
SGND
EXTV
RUN
BG1
CC
LTC3787
D1
VBIAS
INTV
CC
FREQ
V
V
IN
OUT
C
SS
, 0.1ꢀF
C
INT
4.7ꢀF
5V TO 24V
24V, 10A*
C
IN
SS
22ꢀF
PGND
BG2
C
, 15nF
s 2
ITH
D2
C
R
ITH
, 8.66k
ITH
MBOT2
MTOP2
, 0.1ꢀF
B2
C
ITHA
, 220pF
L2
3.3ꢀH
R
SENSE2
4mΩ
BOOST2
SW2
R , 12.1k
A
TG2
VFB
SENSE2
SENSE2
+
–
R
B
232k
+
C
22ꢀF
s 4
OUTA2
C
OUTB2
220ꢀF
3787 F10
C
C
, C : TDK C4532X5R1E226M
, C
OUTB1 OUTB2
IN OUTA1 OUTA2
, C : SANYO, 50CE220LX
L1, L2: PULSE PA1494.362NL
MBOT1, MBOT2, MTOP1, MTOP2: RENESAS HAT2169H
D1, D2: BAS140W
*WHEN V < 8V, MAXIMUM LOAD CURRENT AVAILABLE IS REDUCED.
IN
Figure ±0. High Efficiency 2-Phase 24V Boost Converter
–
SENSE1
SENSE1
ILIM
100k
+
+
C
PGOOD
TG1
INTV
CC
OUTA1
C
OUTB1
220ꢀF
L1
3.3ꢀH
6.8ꢀF
R
MTOP1
MBOT1
SENSE1
4mΩ
× 4
PHASMD
CLKOUT
PLLIN/MODE
SGND
SW1
C
, 0.1ꢀF
B1
BOOST1
EXTV
RUN
BG1
CC
LTC3787
D1
VBIAS
INTV
CC
FREQ
V
V
IN
OUT
C
SS
, 0.1ꢀF
C
INT
4.7ꢀF
5V TO 28V
28V, 8A
C
IN
SS
6.8ꢀF
PGND
BG2
C , 15nF
ITH
× 4
D2
C
R
, 8.66k
ITH
ITH
MBOT2
MTOP2
, 0.1ꢀF
B2
C
, 220pF
ITHA
L2
3.3ꢀH
R
SENSE2
4mΩ
BOOST2
SW2
R , 12.1k
A
TG2
VFB
SENSE2
SENSE2
+
–
R
B
271k
+
C
6.8ꢀF
× 4
OUTA2
C
OUTB2
220ꢀF
3787 F11
C
, C : TDK C4532X7RIH685K
, C
OUTB1 OUTB2
IN OUTA1 OUTA2
C
, C : SANYO, 50CE220LX
L1, L2: PULSE PA1494.362NL
MBOT1, MBOT2, MTOP1, MTOP2: RENESAS HAT2169H
D1, D2: BAS140W
Figure ±±. High Efficiency 2-Phase 28V Boost Converter
3787fc
29
LTC3787
TYPICAL APPLICATIONS
–
SENSE1
100k
+
+
C
SENSE1
PGOOD
TG1
INTV
CC
OUTA1
C
OUTB1
220ꢀF
L1
10.2ꢀH
6.8ꢀF
R
MTOP1
MBOT1
SENSE1
5mΩ
ILIM
× 4
PHASMD
CLKOUT
SW1
C
, 0.1ꢀF
B1
PLLIN/MODE BOOST1
SGND
EXTV
RUN
BG1
CC
LTC3787
D1
VBIAS
INTV
CC
FREQ
V
V
IN
OUT
C
SS
, 0.1ꢀF
C
INT
4.7ꢀF
5V TO 36V
36V, 6A
C
IN
SS
6.8ꢀF
PGND
BG2
C
ITH
, 15nF
× 4
D2
C
R
, 3.57k
ITH
ITH
MBOT2
MTOP2
, 0.1ꢀF
B2
C
, 220pF
ITHA
L2
10.2ꢀH
R
SENSE2
5mΩ
BOOST2
SW2
R , 12.1k
A
TG2
VFB
SENSE2
SENSE2
+
–
R
B
348k
+
C
6.8ꢀF
× 4
OUTA2
C
OUTB2
220ꢀF
3787 F12
C
, C : TDK C4532X7RIH685K
, C
OUTB1 OUTB2
IN OUTA1 OUTA2
C
, C : SANYO, 50CE220LX
L1, L2: PULSE PA2050.103NL
MBOT1, MBOT2, MTOP1, MTOP2: RENESAS RJICO652DPB
D1, D2: BAS170W
Figure ±2. High Efficiency 2-Phase 36V Boost Converter
–
SENSE1
100k
+
+
C
SENSE1
PGOOD
TG1
INTV
CC
OUTA1
C
OUTB1
220ꢀF
L1
16ꢀH
6.8ꢀF
R
MTOP1
MBOT1
SENSE1
8mΩ
ILIM
× 4
PHASMD
CLKOUT
SW1
C
, 0.1ꢀF
B1
PLLIN/MODE
BOOST1
SGND
EXTV
RUN
BG1
CC
LTC3787
D1
VBIAS
INTV
CC
FREQ
V
V
IN
OUT
C , 0.1ꢀF
SS
C
INT
4.7ꢀF
5V TO 38V
48V, 4A
C
IN
SS
6.8ꢀF
PGND
BG2
C , 10nF
ITH
× 4
D2
C
R
, 23.7k
ITH
ITH
MBOT2
MTOP2
, 0.1ꢀF
B2
C
, 220pF
ITHA
L2
16ꢀH
R
SENSE2
8mΩ
BOOST2
SW2
R , 12.1k
A
TG2
VFB
SENSE2
SENSE2
+
–
R
B
475k
+
C
6.8ꢀF
× 4
OUTA2
C
OUTB2
220ꢀF
3787 F13
C
, C : TDK C4532X7RIH685K
, C
OUTB1 OUTB2
IN OUTA1 OUTA2
C
, C : SANYO, 63CE220K
L1, L2: PULSE PA2050.163NL
MBOT1, MBOT2, MTOP1, MTOP2: RENESAS RJK0652DPB
D1, D2: BAS170W
Figure ±3. High Efficiency 2-Phase 48V Boost Converter
3787fc
30
LTC3787
TYPICAL APPLICATIONS
R
R , 53.6, 1%
S1
S2
26.1k
1%
–
SENSE1
C1
0.1ꢀF
+
OUTA1
C
100k
C
OUTB1
+
6.8ꢀF
PGOOD
TG1
INTV
CC
SENSE1
ILIM
220ꢀF
D3
L1
s 4
C3
0.1ꢀF
MTOP1
MBOT1
10.2ꢀH
PHASMD
CLKOUT
SW1
C
, 0.1ꢀF
B1
PLLIN/MODE BOOST1
SGND
INTV
CC
EXTV
RUN
FREQ
BG1
CC
V
IN
LTC3787
R
, 41.2k
D1
FREQ
5V TO 24V
V
OUT
VBIAS
24V, 8A
+
C
INA
INTV
CC
C
INB
220ꢀF
C
SS
, 0.1ꢀF
22ꢀF
C
INT
s 4
4.7ꢀF
SS
PGND
BG2
C
, 15nF
ITH
D2
C
R
ITH
, 8.87k, 1%
ITH
MBOT2
MTOP2
, 0.1ꢀF
C
, 220pF
ITHA
B2
L2
10.2ꢀH
BOOST2
SW2
R
A
12.1k, 1%
TG2
VFB
R
232k
1%
D4
S
C4
0.1ꢀF
+
–
SENSE2
+
C
R
26.1k
1%
OUTA2
S4
C
OUTB2
C2
0.1ꢀF
6.8ꢀF
220ꢀF
s 4
SENSE2
R
, 53.6k, 1%
S3
3787 F14
C
C
C
C
, C
: C4532x7R1H685K
: SANYO 63CE220KX
OUTA1 OUTA2
, C
OUTB1 OUTB2
: TDK C4532X5R1E226M
: SANYO 50CE220AX
INA
INB
L1, L2: PULSE PA2050.103NL
MBOT1, MBOT2, MTOP1, MTOP2: RENESAS RJK0305
D1, D2: BAS140W
D3, D4: DIODES INC. B340B
Figure ±4. High Efficiency 2-Phase 24V Boost Converter with Inductor DCR Current Sensing
3787fc
31
LTC3787
TYPICAL APPLICATIONS
+
–
SENSE1
SENSE1
100k
+
C
PGOOD
TG1
INTV
CC
OUTA1
C
OUTB1
L1
3.3ꢀH
22ꢀF
R
MTOP1
MBOT1
SENSE1
4mΩ
220ꢀF
s 4
ILIM
PHASMD
SW1
C
, 0.1ꢀF
B1
BOOST1
PLLIN/MODE
INTV
CC
SGND
EXTV
RUN
BG1
CC
LTC3787
D1
VBIAS
FREQ
INTV
CC
C
, 0.1ꢀF
SS
C
INT1
4.7ꢀF
SS
PGND
BG2
C
, 15nF
ITH
D2
C
R
ITH
, 8.66k
ITH
MBOT2
MTOP2
, 0.1ꢀF
C
, 220pF
B2
ITHA
L2
3.3ꢀH
R
SENSE2
4mΩ
BOOST2
SW2
R , 12.1k
A
TG2
VFB
–
SENSE2
SENSE2
+
+
+
C
OUTA2
C
+
OUTB2
R
B
CLKOUT
22ꢀF
220ꢀF
232k
s 4
V
V
OUT
IN
24V, 20A*
5V to 24V
C
INA
C
INB
22ꢀF
220ꢀF
s 4
+
–
SENSE1
SENSE1
100k
C
PGOOD
TG1
INTV
CC
OUTA3
C
OUTB3
L3
3.3ꢀH
22ꢀF
R
MTOP3
MBOT3
SENSE3
4mΩ
220ꢀF
s 4
ILIM
SW1
C
, 0.1ꢀF
B3
PHASMD
PLLIN/MODE
SGND
BOOST1
BG1
EXTV
RUN
FREQ
CC
LTC3787
D3
VBIAS
INTV
CC
C
INT2
4.7ꢀF
PGND
BG2
D4
C
SS
MBOT4
MTOP4
, 0.1ꢀF
B4
L4
3.3ꢀH
R
SENSE4
4mΩ
BOOST2
SW2
ITH
TG2
VFB
–
SENSE2
SENSE2
+
C
OUTA4
C
+
OUTB4
CLKOUT
22ꢀF
220ꢀF
3787 F15
s 4
C
C
, C
, C
, C
, C
: TDK C4532X5R1E226M
: SANYO, 50CE220LX
INA OUTA1 OUTA2 OUTA3 OUTA4
, C
, C
, C
, C
INB OUTB1 OUTB2 OUTB3 OUTB4
L1, L2, L3, L4: PULSE PA1494.362NL
MBOT1, MBOT2, MBOT3, MBOT4, MTOP1, MTOP2, MTOP3, MTOP4: RENESAS HAT2169H
D1, D2, D3, D4: BAS140W
*WHEN V < 8V, MAXIMUM LOAD CURRENT AVAILABLE IS REDUCED.
IN
Figure ±5. 4-Phase Single Output Boost Converter
3787fc
32
LTC3787
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
GN Package
28-Lead Plastic SSOP (Narrow .±50 Inch)
(Reference LTC DWG # 05-08-1641 Rev B)
.386 – .393*
(9.804 – 9.982)
.045 .005
.033
(0.838)
REF
28 27 26 25 24 23 22 21 20 19 18 17 1615
.254 MIN
.150 – .165
.229 – .244
.150 – .157**
(5.817 – 6.198)
(3.810 – 3.988)
.0165 .0015
.0250 BSC
1
2
3
4
5
6
7
8
9 10 11 12 13 14
RECOMMENDED SOLDER PAD LAYOUT
.015 .004
.0532 – .0688
(1.35 – 1.75)
.004 – .0098
(0.102 – 0.249)
w 45°
(0.38 0.10)
.0075 – .0098
(0.19 – 0.25)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
.008 – .012
.0250
(0.635)
BSC
GN28 REV B 0212
(0.203 – 0.305)
TYP
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
3. DRAWING NOT TO SCALE
4. PIN 1 CAN BE BEVEL EDGE OR A DIMPLE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
3787fc
33
LTC3787
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
UFD Package
28-Lead Plastic QFN (4mm × 5mm)
(Reference LTC DWG # 05-08-1712 Rev B)
0.70 0.05
4.50 0.05
3.10 0.05
2.50 REF
2.65 0.05
3.65 0.05
PACKAGE OUTLINE
0.25 0.05
0.50 BSC
3.50 REF
4.10 0.05
5.50 0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
PIN 1 NOTCH
R = 0.20 OR 0.35
× 45° CHAMFER
2.50 REF
R = 0.115
TYP
R = 0.05
TYP
0.75 0.05
4.00 0.10
(2 SIDES)
27
28
0.40 0.10
PIN 1
TOP MARK
(NOTE 6)
1
2
5.00 0.10
(2 SIDES)
3.50 REF
3.65 0.10
2.65 0.10
(UFD28) QFN 0506 REV B
0.25 0.05
0.50 BSC
0.200 REF
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X).
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3787fc
34
LTC3787
REVISION HISTORY
REV
DATE
DESCRIPTION
PAGE NUMBER
A
12/10 Updated PGND, BG2, BG1, INTV and EXTV Pin numbers
10
CC
CC
Updated Block Diagram
Updated Figures 11, 12, 13
Updated Related Parts
11
29, 30
36
B
C
9/11
4/12
Updated graphs on TA01b, G02, G09, G10, G11, G13, G14, G15, G18, G19, G22, and G26.
Updated the Storage Temperature Range
1, 5, 6, 7, 8, 9
2
Updated Topside MOSFET Driver Supply (C , D ) section
22
B
B
Updated Related Parts List
Added H and MP grades
36
2, 4
3787fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
35
LTC3787
TYPICAL APPLICATION
I
IN
C
IN
12V
I
1
0°
I
I
PHASMD
BG1
TG1
1
2
BOOST: 24V, 5A
LTC3787
I
I
2
180°
90°
BG2
TG2
BOOST: 24V, 5A
BOOST: 24V, 5A
CLKOUT
+90°
I
I
3
4
24V, 20A
3
90,270
C
I
COUT
OUT
CLKOUT
PHASMD
BG1
TG1
LTC3787
I
4
I*
IN
270°
BG2
TG2
BOOST: 24V, 5A
I*
COUT
REFER TO FIGURE 15 FOR APPLICATION CIRCUITS
* RIPPLE CURRENT CANCELLATION INCREASES THE RIPPLE
FREQUENCY AND REDUCES THE RMS INPUT/OUTPUT RIPPLE
CURRENT, THUS SAVING INPUT/OUTPUT CAPACITORS
3787 F16
Figure ±6. PolyPhase Application
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC3788/LTC3788-1 Multiphase, Dual Output Synchronous Step-Up
Controller
4.5V (Down to 2.5V After Start-Up) ≤ V ≤ 38V, V
Up to 60V, 50kHz to
IN
OUT
900kHz Fixed Operating Frequency, 5mm × 5mm QFN-32, SSOP-28
LTC3786
Low IQ Synchronous Step-Up Controller
4.5V (Down to 2.5V After Start-Up) ≤ V ≤ 38V, V Up to 60V, 50kHz to
IN
OUT
900kHz Fixed Operating Frequency, 3mm × 3mm QFN-32, MSOP-16E
LTC3862/LTC3862-1 Multiphase, Dual Channel Single Output Current
Mode Step-Up DC/DC Controller
4V ≤ V ≤ 36V, 5V or 10V Gate Drive, 75kHz to 500kHz Fixed Operating
IN
Frequency, SSOP-24, TSSOP-24, 5mm × 5mm QFN-24
LT3757/LT3758
Boost, Flyback, SEPIC and Inverting Controller
2.9V ≤ V ≤ 40V/100V, 100kHz to 1MHz Fixed Operating Frequency,
IN
3mm × 3mm DFN-10 and MSOP-10E
LTC1871/LTC1871-1/ Wide Input Range, No R
Low Quiescent Current 2.5V ≤ V ≤ 36V, 50kHz to 1MHz Fixed Operating Frequency, I = 250ꢀA ,
SENSE
IN
Q
LTC1871-7
LTC3859
Flyback, Boost and SEPIC Controller
MSOP-10
Low I , Triple Output Buck/Buck/Boost Synchronous All Outputs Remain in Regulation Through Cold Crank, 4.5V (Down to
Q
DC/DC Controller
2.5V After Start-Up) ≤ V ≤ 38V, V
Up to 24V, V
OUT(BUCKS) OUT(BOOST)
IN
Up to 60V, I = 55ꢀA
Q
LTC3789
High Efficiency Synchronous 4-Switch Buck-Boost
DC/DC Controller
4V ≤ V ≤ 38V, 0.8V ≤ V
≤ 38V, 4mm × 5mm QFN-28 and SSOP-2
IN
OUT
3787fc
LT 0412 REV C • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
36
●
●
© LINEAR TECHNOLOGY CORPORATION 2010
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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